CPU STA CAD Engineer - Santa Clara, California, United States of America
$198,700 - $298,100 USD yearly
Originally posted 17 August 2026 by the employer.
Work on custom CPUs that push the envelope on performance, energy efficiency and scalability.
About the role
What you'll do
- Architect and recommend methodology improvements for silicon power, performance, and area.
- Maintain, support, and debug STA and timing closure (ECO) flows, and resolve project-specific issues.
- Provide methodology guidance and tools/flows support to worldwide CPU physical design teams.
- Work with EDA vendors to define roadmaps and resolve tool issues.
What you'll need
- 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience with a Bachelor's degree.
- Industry experience of Static Timing Analysis (STA) on technology nodes.
- Programming/Scripting skills (Python and Tcl).
- Experienced in generating/optimizing/automating timing ECO closure.
- Detailed understanding of STA concepts (e.g.: LVF/CCS/SSI/NBTI).
- Synthesis/PnR experience with a focus on PPA optimization.
Nice to have
- Web/Database/Dashboards/Visualization experience.
- Experience applying AI techniques to EDA workflows, including log analysis, root-cause investigation, metrics mining, knowledge retrieval, and automated generation of scripts, documentation, and test collateral.
Skills: STA, timing closure, ECO flows, methodology improvements, EDA vendors, scripting
This role has been open 59 days — well below the 73-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
675
|
Median days open
73 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (675 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 675 |
| Open roles in the wider Physical Implementation family | 161 | 1449 · 110 employers |
| Median days open | 74 d | 73 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: STA, timing closure, ECO flows, methodology improvements, EDA vendors, scripting
Who's hiring in this category
- Cadence Design Systems · 153 open roles · median 169 d
- Synopsys · 63 open roles · median 38 d
- Micron Technology · 44 open roles · median 46 d
- Qualcomm (this employer) · 36 open roles · median 74 d
- GlobalFoundries · 33 open roles · median 37 d
- Keysight Technologies · 32 open roles · median 71 d
How we counted: 675 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.