CPU Server Physical Design Timing Engineer
$167,100 - $250,700 USD yearly
Originally posted 7 August 2026 by the employer.
Join our team focused on Oryon CPU Cores.
About the role
This role involves defining, developing, and driving CPU timing closure for Oryon CPU Cores. You will work with microarchitecture and RTL design teams to develop timing constraints and implement designs to meet aggressive power, area, and performance goals.
What you'll do
- Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
- Conduct timing analysis, validation, and debug across multiple PVT conditions using PT/Tempus.
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Identify root causes of timing miscorrelation at different design levels in functional and test modes and propose solutions.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Develop automation scripts within STA/PD tools for methodology development.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of hardware engineering experience, OR Master's degree in a related field and 3+ years of experience, OR PhD in a related field and 2+ years of experience.
- Experience in design automation using TCL/Perl/Python.
- Familiarity with digital flow design implementation RTL to GDS: ICC, Innovous, PT/Tempus.
Nice to have
- Expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
- Hands-on experience with STA tools - Primetime, Tempus.
- Experience in driving timing convergence at Chip-level and Hard-Macro level.
- In-depth knowledge of cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
- Expertise in scripting languages – TCL, Perl, Python.
- Basic knowledge of device physics.
Skills: timing closure, STA, Primetime, Tempus, CPU cores
This role has been open 70 days — well above the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
659
|
Median days open
60 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (659 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 119 | 659 |
| Open roles in the wider Physical Implementation family | 161 | 1442 · 110 employers |
| Median days open | 44 d | 60 d (−16 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: timing closure, STA, Primetime, Tempus, CPU cores
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 45 d
- AMD · 63 open roles · median 24 d
- NVIDIA · 37 open roles · median 72 d
- Synopsys · 37 open roles · median 32 d
- Intel Corporation · 36 open roles · median 11 d
- Broadcom · 30 open roles · median 97 d
How we counted: 659 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.