CPU Server Physical Design Engineer
$147,900 - $221,900 USD yearly
Originally posted 13 October 2026 by the employer.
Work on CPU designs with a critical impact on industries worldwide.
About the role
As a CPU Server Physical Design Engineer, you will be responsible for leading CPU design efforts that have a critical impact on industries across the world. You will collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units.
What you'll do
- Apply knowledge of computer architecture, micro-architecture, logic design, circuits, and/or physical design to develop and verify high performance and low power CPU designs.
- Anticipate, identify, and solve problems to ensure design completeness, functionality, power, and performance.
- Collaborate across teams to define requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities) to accomplish product goals.
- Evaluate the design process from conceptualization to productization (i.e., architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation) that meet customer and industry standards.
- Write detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details) for CPU designs.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience; OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of work experience; OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 2 years of work experience with high-performance microprocessor design.
- 2 years of work experience with high level programming (e.g., C, C++), scripting language programming (e.g., Perl, Python).
- 2 years of work experience with simulators and/or waveform debugging tools (e.g., Verilog, VHDL).
- 2 years of work experience with industry standard tools for synthesis place and/or route and design verification.
- 2 years of work experience with simulation, emulation, formal verification, or silicon validation.
- 2 years of experience in creating functional models, checkers, test plans, and/or test generation.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 1 year experience working in a large matrixed organization.
Skills: CPU designs, physical design, synthesis place and/or route, logic design, micro-architecture
This role has been open 0 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 123 | 664 |
| Open roles in the wider Physical Implementation family | 170 | 1463 · 108 employers |
| Median days open | 44 d | 63 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU designs, physical design, synthesis place and/or route, logic design, micro-architecture
Who's hiring in this category
- Qualcomm (this employer) · 122 open roles · median 46 d
- AMD · 59 open roles · median 21 d
- NVIDIA · 39 open roles · median 68 d
- Broadcom · 35 open roles · median 93 d
- Synopsys · 35 open roles · median 44 d
- Intel Corporation · 29 open roles · median 14 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.