CPU Server Physical Design Clock Engineer
$142,200 - $213,400 USD yearly
Originally posted 7 July 2026 by the employer.
About the role
As a Physical Design Clock Engineer, you will work with microarchitecture, RTL design, CAD, block-level, and top-level physical design teams to develop clocking solutions for CPUs.
What you'll do
- Perform jitter analysis and measurements and provide feedback to block-level and top-level physical design engineers on key fixes required. - Work with design teams to understand, implement, and validate CPU clocking. - Drive the overall clock generation and distribution methodology of the CPU. - Work with CAD and block-level designers to implement clocking techniques for optimizing skew and power.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of engineering experience, or a Master's degree with 1+ year of experience, or a PhD. - Experience in all aspects of construction and analysis of low-skew and low-power clock generation and distribution. - Experience in clock H-tree, mesh, spines, and CTS implementations. - Understanding of device physics, RC delay, and electrical aspects. - Proficiency in SPICE simulation and analysis for circuit design and verification.
Nice to have
- Master's degree in Electrical Engineering with 4 years of practical experience. - Experience in chip physical design, standard cell optimizations, and clock construction. - Experience defining clock methodology across various designs. - Experience in deep submicron process technology nodes. - Proficiency in PLL specifications, clock skew estimation, and jitter measurements.
Skills: physical design, clock construction, jitter analysis, clock skew, PLL specifications
This role has been open 105 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
656
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (656 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 119 | 656 |
| Open roles in the wider Physical Implementation family | 162 | 1464 · 110 employers |
| Median days open | 44 d | 61 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: physical design, clock construction, jitter analysis, clock skew, PLL specifications
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 44 d
- AMD · 61 open roles · median 26 d
- Synopsys · 38 open roles · median 35 d
- Intel Corporation · 36 open roles · median 14 d
- NVIDIA · 36 open roles · median 70 d
- Broadcom · 32 open roles · median 100 d
How we counted: 656 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.