CPU Server FV/CLP/STA engineer
$147,900 - $221,900 USD yearly
Originally posted 8 September 2026 by the employer.
About the role
As a CPU Server FV/CLP/STA engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, and equipment.
What you'll do
- Handle complex data path oriented multi-million gate synthesis.
- Develop constraints for multi-clock domains hierarchical/flat timing analysis.
- Perform multi-power domain synthesis and structural power checks using CLP.
- Conduct Formal verification and debug issues/aborts.
- Perform Pre-layout STA and analyze timing reports and generate timing ECOs.
- Analyze trade-offs and recipes for timing, area, power, and congestion.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience; OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of related work experience; OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Experience in Physical synthesis using tools like DC, Genus, or Fusion Compiler.
- Working knowledge in multi-power domain synthesis and structural power checks using CLP.
- Hands-on experience in Formal verification with strong debugging skills.
- Good working knowledge in Pre-layout STA and analyzing timing reports and generating timing ECOs.
- Knowledge on analyzing trade-offs and recipes for timing/area/power/congestion.
- Exposure in TCL scripting for usage in Synthesis/STA.
Nice to have
- Knowledge on Hierarchical STA with Hyperscale.
Skills: Physical synthesis, DC, Genus, Fusion Compiler, timing analysis, CLP, Formal verification, Pre-layout STA
This role has been open 36 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
661
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (661 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 124 | 661 |
| Open roles in the wider Physical Implementation family | 171 | 1469 · 108 employers |
| Median days open | 44 d | 61 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Physical synthesis, DC, Genus, Fusion Compiler, timing analysis, CLP
Who's hiring in this category
- Qualcomm (this employer) · 123 open roles · median 44 d
- AMD · 59 open roles · median 22 d
- NVIDIA · 39 open roles · median 69 d
- Synopsys · 37 open roles · median 29 d
- Broadcom · 34 open roles · median 94 d
- Intel Corporation · 30 open roles · median 12 d
How we counted: 661 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.