CPU Server Floorplan and Integration Engineer
$142,200 - $213,400 USD yearly
Originally posted 7 July 2026 by the employer.
About the role
As a CPU Floorplan and Integration Engineer, you will collaborate with microarchitecture, RTL design, and physical design teams to design, floorplan, and integrate CPU designs to meet power, area, and performance goals. The role focuses on developing server-class CPU solutions for data center applications.
What you'll do
- Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP integration, power/ground generation, and pin assignment. - Oversee full chip floorplan, area optimizations, block partitioning, and pin assignments. - Manage chip-level place and route, and finalize the CPU database for construction and verification. - Coordinate custom layout integration and collaborate with external teams to fulfill IP technical and delivery requirements. - Develop workflows for chip integration and analysis while ensuring designs are validated for functional and electrical robustness.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of hardware engineering experience, or a Master's degree with 1+ year experience, or a PhD. - Proficiency in synthesis, place and route, and signoff timing/power analysis. - Expertise in block-level implementation, full chip floorplanning, and power grid planning. - In-depth understanding of extraction, static timing analysis (STA), and electromigration and IR drop (EMIR) flows and methodologies. - Experience in physical design, integration, and verification of large processor and system-on-chip (SoC) designs. - Knowledge of low power and high-performance design methodologies alongside circuit and layout design principles.
Nice to have
- Experience in deep submicron process technology nodes. - Experience as a key technical lead driving development and delivery of physical design databases. - Solid understanding of industry standard tools for synthesis, place & route, and tapeout flows.
Skills: floorplanning, place and route, signoff timing/power analysis, CPU physical design, IP integration
This role has been open 105 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
656
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (656 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 119 | 656 |
| Open roles in the wider Physical Implementation family | 162 | 1464 · 110 employers |
| Median days open | 44 d | 61 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: floorplanning, place and route, signoff timing/power analysis, CPU physical design, IP integration
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 44 d
- AMD · 61 open roles · median 26 d
- Synopsys · 38 open roles · median 35 d
- Intel Corporation · 36 open roles · median 14 d
- NVIDIA · 36 open roles · median 70 d
- Broadcom · 32 open roles · median 100 d
How we counted: 656 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.