CPU RTL Methodology Engineer - Santa Clara, California, United States of America
$198,700 - $298,100 USD yearly
Originally posted 6 April 2026 by the employer.
Build scalable automation tooling and workflows for CPU RTL development across Verilog/SystemVerilog environments.
About the role
This role operates at the intersection of RTL design and CAD automation, supporting RTL development and debug workflows across CPU design teams. You will define methodologies and build automation solutions to streamline RTL workflows, verification, and regression systems.
What you'll do
- Define and develop methodologies to build scalable, efficient CPU designs. - Support RTL development and debug workflows across CPU design teams, triaging and resolving RTL issues. - Maintain and enhance RTL databases and repositories using GIT and other version control systems. - Develop and maintain automation scripts and tools primarily in Python to improve RTL workflows, verification, and regression systems. - Interface with CAD teams to align RTL tooling with broader design infrastructure. - Contribute to continuous integration and build systems for RTL environments, documenting workflows, tools, and best practices.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of relevant experience (or Master's with 5+ years, or PhD with 4+ years). - Strong experience in RTL design (Verilog/SystemVerilog) and an understanding of CPU microarchitecture. - Solid knowledge of RTL databases and version control systems (GIT). - Advanced scripting skills in Python, alongside experience with CAD tools and automation frameworks in a hardware design environment. - Familiarity with CI/CD pipelines and build systems for RTL.
Skills: RTL design, CPU microarchitecture, RTL databases, version control systems (GIT), Python scripting, CAD tools, hardware design environment, CI/CD pipelines, build systems for RTL, Verilog/SystemVerilog
This role has been open 200 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1083
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1083 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 158 | 1083 |
| Open roles in the wider Digital Design & Verification family | 420 | 3310 · 115 employers |
| Median days open | 61 d | 64 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL design, CPU microarchitecture, RTL databases, version control systems (GIT), Python scripting, CAD tools
Who's hiring in this category
- Qualcomm (this employer) · 160 open roles · median 61 d
- Synopsys · 87 open roles · median 37 d
- AMD · 77 open roles · median 43 d
- Analog Devices · 49 open roles · median 54 d
- NXP Semiconductors · 42 open roles · median 93 d
- NVIDIA · 40 open roles · median 64 d
How we counted: 1083 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.