CPU Physical Design Timing Engineer (Austin, TX)
$122,500 - $183,700 USD yearly
Originally posted 29 June 2026 by the employer.
Drive CPU timing closure and STA signoff for Oryon CPU Cores on N2/N3 nodes.
About the role
As a CPU Physical Design Timing Engineer, you will define, develop, and drive CPU timing closure for Oryon CPU Cores. The role focuses on N2/N3 process nodes, developing timing constraints and STA signoff flows in collaboration with microarchitecture and implementation teams.
What you'll do
- Execute STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores. - Perform timing analysis, validation, and debug across multiple PVT conditions using PrimeTime and Tempus. - Run PrimeTime and Tempus for STA flow optimization and Spice to STA correlation. - Root cause timing miscorrelation at different design levels in functional and test modes, and propose solutions. - Develop automation scripts using TCL, Perl, or Python to enable CPU STA signoff flows, infrastructure, and methodologies. - Interface with microarchitecture, RTL design, and CPU implementation teams to develop timing constraints and meet power, area, and performance goals.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of relevant experience, a Master's degree with 1+ year of experience, or a PhD. - Automation skills using TCL, Perl, or Python to develop STA signoff scripts and tooling. - Experience with STA tools such as PrimeTime or Tempus. - Familiarity with digital design implementation flows from RTL to GDS using ICC, ICC2, or Innovus.
Nice to have
- Expertise in STA timing analysis concepts, including AOCV/POCV, CTS, timing constraints, latch transparency handling, and 0-cycle/multi-cycle path handling. - Experience driving timing convergence at the chip level and hard-macro level. - In-depth knowledge of crosstalk noise, signal integrity, layout parasitic extraction, and feedthrough handling. - History of developing timing automation frameworks, tools, or utilities. - Basic knowledge of device physics.
Skills: CPU timing closure, physical design, timing constraints, STA setup, Prime-time, Tempus, ASIC back-end, ICC2, Innovus
This role has been open 114 days — well above the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 119 | 664 |
| Open roles in the wider Physical Implementation family | 162 | 1464 · 110 employers |
| Median days open | 44 d | 62 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU timing closure, physical design, timing constraints, STA setup, Prime-time, Tempus
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 45 d
- AMD · 61 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 67 d
- Synopsys · 38 open roles · median 36 d
- Broadcom · 35 open roles · median 101 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.