CPU Physical Design Timing Engineer
$198,700 - $298,100 USD yearly
Originally posted 2 September 2026 by the employer.
Define, develop, and drive CPU timing closure for Oryon CPU Cores using N2/N3 technology nodes.
About the role
In this role, you will define, develop, and drive CPU timing closure for Oryon CPU Cores. You will work with microarchitecture and RTL design teams to develop timing constraints and drive implementation to meet power, area, and performance goals on N2/N3 technology nodes.
What you'll do
- Set up, converge, review, and sign off on STA for multi-mode, multi-voltage domain designs of Oryon CPU Cores.
- Analyze, validate, and debug timing across multiple PVT conditions using PT/Tempus.
- Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
- Identify the root cause of timing miscorrelation at different design levels in functional and test mode and propose solutions.
- Evaluate multiple timing methodologies/tools on different designs and technology nodes.
- Code scripts used with STA native tools to enable CPU timing infrastructure and methodology.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience; OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of relevant experience; OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of relevant experience.
- Excellent automation skills using TCL/Perl/Python.
- Ability to develop/work on automation scripts to develop CPU STA signoff flow/methodology.
- Familiarity with digital flow design implementation RTL to GDS: ICC, Innovus, PT/Tempus.
Nice to have
- Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
- Hands-on experience with STA tools - Primetime, Tempus.
- Experience in driving timing convergence at Chip-level and Hard-Macro level.
- In-depth knowledge of crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
- Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus).
- Basic knowledge of device physics.
- History of framework/tool/utility development.
Skills: CPU timing closure, STA, Primetime, Tempus, timing constraints, ASIC back-end
This role has been open 42 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
661
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (661 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 124 | 661 |
| Open roles in the wider Physical Implementation family | 171 | 1466 · 108 employers |
| Median days open | 44 d | 61 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU timing closure, STA, Primetime, Tempus, timing constraints, ASIC back-end
Who's hiring in this category
- Qualcomm (this employer) · 123 open roles · median 44 d
- AMD · 59 open roles · median 22 d
- NVIDIA · 39 open roles · median 69 d
- Synopsys · 37 open roles · median 29 d
- Broadcom · 34 open roles · median 94 d
- Intel Corporation · 30 open roles · median 12 d
How we counted: 661 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.