CPU Physical Design Engineer - Austin, Texas, United States of America, United States
$211,900 - $317,900 USD yearly
Originally posted 14 September 2026 by the employer.
About the role
As a CPU Physical Design Engineer, you will lead innovative Central Processing Unit (CPU) design efforts. You will be involved in designing, verifying, and implementing multi-core CPU operations.
What you'll do
- Develop and verify high performance and low power CPU designs leveraging expertise in computer architecture, micro-architecture, logic design, circuits, and/or physical design.
- Identify and solve complex problems to ensure design completeness, functionality, power, and performance.
- Collaborate with cross-functional stakeholders to define requirements, specifications, and trade-offs.
- Evaluate all aspects of the design process from conceptualization to productization, including architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation.
- Write detailed technical documentation for complex CPU designs and review documentation from experienced engineers.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 8+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience; OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 7+ years of relevant experience; OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of relevant experience.
Nice to have
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 14 years of work experience with high-performance microprocessor design.
- 14 years of work experience with high level programming (e.g., C, C++), scripting language programming (e.g., Perl, Python, etc.).
- 14 years of work experience with simulators and/or waveform debugging tools (e.g., Verilog, VHDL, etc.).
- 14 years of work experience with industry standard tools for synthesis place and/or route and design verification.
- 14 years of work experience with simulation, emulation, formal verification, or silicon validation.
- 14 years of experience in creating functional models, checkers, test plans, and/or test generation.
- 3 years experience working in a large matrixed organization.
- 2 years in a technical leadership role.
- 1 year of work experience in a role requiring interaction with senior leadership.
Skills: CPU design, physical design, power, performance, place and route, design verification
This role has been open 30 days — well below the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
661
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (661 roles · 80 employers) |
|---|---|---|
| Open roles in this specialty | 124 | 661 |
| Open roles in the wider Physical Implementation family | 171 | 1470 · 108 employers |
| Median days open | 44 d | 61 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU design, physical design, power, performance, place and route, design verification
Who's hiring in this category
- Qualcomm (this employer) · 123 open roles · median 44 d
- AMD · 59 open roles · median 22 d
- NVIDIA · 39 open roles · median 69 d
- Synopsys · 37 open roles · median 29 d
- Broadcom · 34 open roles · median 94 d
- Intel Corporation · 30 open roles · median 12 d
How we counted: 661 open Physical Design (Physical Design) roles from 80 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.