CPU Physical Design CAD Engineer (Sr Staff) - Santa Clara, California, United States of America
$209,300 - $313,900 USD yearly
Originally posted 6 October 2026 by the employer.
About the role
As a CPU Physical Design CAD Engineer, you will build and support implementation tools and flows for custom CPUs.
What you'll do
- Develop, integrate, and release new features in the high-performance place-and-route CAD flow.
- Architect and recommend methodology improvements to optimize silicon power, performance, and area.
- Maintain, support, and debug implementation flows, and resolve project-specific issues.
- Work with worldwide CPU physical design teams to provide methodology guidance, tools/flows support, and achieve class-leading PPA.
- Collaborate with EDA vendors to define roadmaps and resolve tool issues.
What you'll need
- Ten years of hands-on experience in place-and-route of high-performance chips in a design or CAD role.
- High level of proficiency in Tcl and Python.
- Experience with automation.
- Experience with Physical Design tasks including place-and-route, analysis, timing sign-off, and PDV.
- Experience with advanced technology nodes (5nm or lower).
- Solid understanding of digital design, timing analysis, and physical verification.
- Strong user of industry-standard place-and-route tools such as Cadence Innovus.
- Proven track record of managing and regressing place-and-route flows.
Skills: CAD flow, place-and-route, Tcl, Python, Cadence Innovus
This role has been open 2 days — well below the 79-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
704
|
Median days open
79 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (704 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 42 | 704 |
| Open roles in the wider Physical Implementation family | 180 | 1488 · 107 employers |
| Median days open | 60 d | 79 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: CAD flow, place-and-route, Tcl, Python, Cadence Innovus
Who's hiring in this category
- Cadence Design Systems · 163 open roles · median 162 d
- Synopsys · 59 open roles · median 36 d
- Micron Technology · 44 open roles · median 107 d
- Qualcomm (this employer) · 42 open roles · median 60 d
- NVIDIA · 41 open roles · median 73 d
- GlobalFoundries · 30 open roles · median 51 d
How we counted: 704 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 9 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.