CPU Micro-Architecture and RTL Design Engineer (RISC-V) - Santa Clara, California, United States of America
$167,100 - $250,700 USD yearly
Originally posted 13 July 2026 by the employer.
Develop CPU RTL targeted for high performance, low power devices using the RISC-V architecture.
About the role
As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to conceive micro-architecture and support architecture and product definition early in the product life cycle. The role focuses on CPU RTL development for high-performance, low-power devices using the RISC-V architecture.
What you'll do
- Explore high-performance strategies in collaboration with the CPU modeling team. - Drive microarchitecture development and specification from high-level architectural exploration through detailed specification. - Own RTL design development, assessment, and refinement to meet power, performance, area, and timing goals. - Support the design verification team in executing the functional verification strategy. - Assist in performance verification to ensure the RTL design meets target performance metrics. - Collaborate with multi-functional engineering teams to implement and validate physical design across timing, area, reliability, and testability.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of hardware, software, electrical, or systems engineering experience (or Master's degree with 3+ years, or PhD with 2+ years). - Experience in hardware engineering, systems engineering, or related technical domains.
Nice to have
- Knowledge of microprocessor architecture, including instruction fetch and decode, branch prediction, instruction scheduling, register renaming, out-of-order execution, integer and floating point execution, load/store execution, prefetching, cache, or memory subsystems. - Knowledge of Verilog and/or VHDL, alongside experience with simulators and waveform debugging tools. - Knowledge of logic design principles along with timing and power implications. - Understanding of low power microarchitecture techniques and high-performance trade-offs in CPU microarchitecture. - Experience using a scripting language such as Perl or Python.
This role has been open 98 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1045
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1045 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 150 | 1045 |
| Open roles in the wider Digital Design & Verification family | 398 | 3244 · 116 employers |
| Median days open | 57 d | 62 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm (this employer) · 148 open roles · median 58 d
- Synopsys · 85 open roles · median 34 d
- AMD · 72 open roles · median 40 d
- Analog Devices · 49 open roles · median 52 d
- NVIDIA · 42 open roles · median 62 d
- NXP Semiconductors · 42 open roles · median 88 d
How we counted: 1045 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.