CPU Emulation Engineer
$167,100 - $250,700 USD yearly
Originally posted 15 July 2026 by the employer.
Architect and develop test bench infrastructure in C/C++ and SystemVerilog for CPU emulation platforms.
About the role
As a CPU Emulation Engineer, you will work as part of the CPU verification team to deliver emulation-based solutions across CPU RTL, performance, verification, and software disciplines.
What you'll do
- Architect and develop test bench infrastructure in C/C++ and SystemVerilog for enabling CPU emulation across different platforms. - Develop verification methodology, ensuring a scalable and portable environment across simulation and emulation. - Debug emulation performance and area issues to efficiently use emulation resources. - Develop environments to run verification test cases, OS boot, performance benchmarks, and other vectors. - Develop debugging methodology to enable root causing of CPU functional and performance issues. - Execute verification plans, including design bring-up, DV environment bring-up, regression enabling, and test failure debug.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of hardware/software/systems engineering experience (or Master's degree with 3+ years, or PhD with 2+ years). - Experience working with CPU verification and delivering emulation-based solutions. - Experience developing test benches using C/C++ and SystemVerilog.
Nice to have
- 5+ years of experience with emulation platforms such as Palladium, ZeBu, Veloce, or FPGAs. - Experience synthesizing and optimizing designs and verification components developed in synthesizable Verilog. - Experience with C/C++ DPI transactors and monitors. - Scripting experience using Perl, Python, or shell scripts, including packaging workloads for cloud. - Experience debugging RISC-V CPU based designs and knowledge of RISC-V programmers' models. - Experience with Linux boot, firmware aspects, and CPU micro-architecture.
Skills: CPU emulation, test bench infrastructure, verification methodology, Palladium, Zebu, Veloce, Systemverilog
This role has been open 96 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1214
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1214 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 114 | 1214 |
| Open roles in the wider Digital Design & Verification family | 398 | 3244 · 116 employers |
| Median days open | 41 d | 64 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: CPU emulation, test bench infrastructure, verification methodology, Palladium, Zebu, Veloce, Systemverilog
Who's hiring in this category
- Qualcomm (this employer) · 113 open roles · median 40 d
- AMD · 96 open roles · median 53 d
- NVIDIA · 84 open roles · median 61 d
- Synopsys · 65 open roles · median 35 d
- SiFive · 55 open roles · median 77 d
- Cadence Design Systems · 50 open roles · median 119 d
How we counted: 1214 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.