CPU DFT Engineer
$142,200 - $213,400 USD yearly
Originally posted 9 June 2026 by the employer.
About the role
As a DFT Engineer, you will work with chip architects, chip designers, implementation engineers, and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. You will contribute to a ground-up implementation of a new chip architecture.
What you'll do
- Create test vectors or oversee their creation. - Validate that DFT requirements are being met across the design. - Work with designers to increase test coverage, debug observability, and flexibility. - Verify post-PD designs meet DFT requirements. - Work with test personnel, stepping in to run tests when needed.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of relevant engineering experience (or Master's degree and 1+ year, or PhD). - Practical experience with ASIC test, DFT, and debug. - Experience using Verilog or VHDL for digital ASIC design. - Experience using Mentor Tessent tools. - Experience defining and implementing SOC-level verification on large designs. - Scripting experience in TCL, Perl/Python, and Shell scripting.
Nice to have
- Hands-on expertise with commercial test generation tools for large complex designs. - Knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, MBIST, and LBIST. - Experience running test compression software.
Skills: ASIC test, DFT, Tessent, ATPG, MBIST
This role has been open 200 days — well above the 64-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
246
|
Median days open
64 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (246 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 26 | 246 |
| Open roles in the wider Digital Design & Verification family | 420 | 3310 · 115 employers |
| Median days open | 74 d | 64 d (+10 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: ASIC test, DFT, Tessent, ATPG, MBIST
Who's hiring in this category
- AMD · 36 open roles · median 46 d
- Qualcomm (this employer) · 26 open roles · median 74 d
- NVIDIA · 23 open roles · median 43 d
- NXP Semiconductors · 19 open roles · median 48 d
- Synopsys · 15 open roles · median 31 d
- Intel Corporation · 11 open roles · median 54 d
How we counted: 246 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.