CPU Design Engineer - San Jose, California, United States
$133,200 - $192,800 USD yearly
Originally posted 29 September 2026 by the employer.
This role focuses on architecting processor pipelines optimized for Altera FPGA architectures.
About the role
This role involves the micro-architecture, RTL design, and implementation of high-performance, area-efficient Soft CPU cores. The focus is on architecting processor pipelines that are natively optimized to leverage Altera FPGA architectures, such as our RISC-V-based Nios V ecosystem.
What you'll do
- Micro-architect, design, and implement Soft CPU cores using SystemVerilog/Verilog for Altera FPGA architectures.
- Optimize Performance, Power, and Area (PPA) for processor pipelines around FPGA-specific constraints.
- Manage floorplanning, placement constraints, and timing closure through Altera's proprietary tool flows.
- Implement features for configurable soft cores, including instruction set extensions, custom instructions, and variable cache configurations.
- Collaborate with Design Verification (DV) teams for robust simulation environments and hardware validation.
What you'll need
- 3+ years of digital design experience with a specific focus on CPU/Processor RTL design and FPGA implementation.
- Advanced proficiency in SystemVerilog or Verilog for FPGA synthesis.
- Strong understanding of processor pipeline design, hazard handling, branch prediction, and memory hierarchy (caches, tightly-coupled memories).
- Deep hands-on proficiency with Altera Quartus Prime Pro, including Platform Designer (Qsys), TimeQuest Timing Analyzer, and Signal Tap or similar EDA software.
Nice to have
- In-depth familiarity with the open-source RISC-V ISA specification and custom instruction insertion.
- Experience with standard FPGA on-chip interfaces like Avalon Memory-Mapped / Streaming and AMBA AXI interfaces.
- Knowledge of compiler toolchains (GCC, LLVM), assembly programming, and embedded C debugging.
- Proficiency in Python, Tcl, or Shell scripting to automate FPGA compilation and regression workflows.
Skills: Soft CPU Design Engineer, micro-architecture, RTL design, FPGA architectures, processor pipelines, SystemVerilog/Verilog
This role has been open 11 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1019
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Altera | All employers we track in this specialty (1019 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 1019 |
| Open roles in the wider Digital Design & Verification family | 23 | 3166 · 114 employers |
| Median days open | 85 d | 60 d (+25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Soft CPU Design Engineer, micro-architecture, RTL design, FPGA architectures, processor pipelines, SystemVerilog/Verilog
Who's hiring in this category
- Qualcomm · 139 open roles · median 60 d
- Synopsys · 86 open roles · median 24 d
- AMD · 73 open roles · median 34 d
- Analog Devices · 50 open roles · median 41 d
- NXP Semiconductors · 48 open roles · median 78 d
- NVIDIA · 46 open roles · median 64 d
How we counted: 1019 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.