CPU Core Staff DFT Engineer - CA, Santa Clara, United States
Verification, Validation & Test
Originally posted 11 September 2026 by the employer.
About the role
This work is a key contributor to delivering a high-quality design and can improve AMD’s operating expenses.
What you'll do
- Own ATPG/DFT responsibilities for high-performance cores.
- Debug low coverage, DRC violation fixes.
- Debug complex test pattern issues and simulation failures.
- Support Silicon bring-up activities.
- Participate in post-silicon debug.
- Work closely with architecture, IP design, physical design, and product engineering teams.
What you'll need
- Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
- Proficient in logic design using Verilog.
- Comfortable in Linux environment and writing/using scripting languages such as Perl, TCL.
- Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST.
- Bachelor's in Electrical Engineering/Computer Engineering.
Nice to have
- Hands-on expertise with commercial test generation tools for large complex designs.
- Strong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE standards like IEEE 1149.1, 1500, and 1687.
- Good understanding of MBIST and LBIST implementations.
- Experience with Tessent Scan/ATPG flows.
- Direct experience in silicon bring-up, debug, and validation of DFT features on ATE.
- Experience with 7nm or smaller process nodes.
- Experience in using Agentic AI to develop flows, debug issues and compress timelines for deliverables.
Market context
This role has been open 33 days — well below the 56-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
250
|
Median days open
56 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (250 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 40 | 250 |
| Open roles in the wider Digital Design & Verification family | 255 | 3191 · 115 employers |
| Median days open | 41 d | 56 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Who's hiring in this category
- AMD (this employer) · 40 open roles · median 41 d
- NVIDIA · 25 open roles · median 41 d
- Qualcomm · 24 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 63 d
- Synopsys · 13 open roles · median 23 d
- Micron Technology · 11 open roles · median 54 d
How we counted: 250 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.