CPU Core Design Verification Testbench Lead - Austin, Texas, United States
Originally posted 22 May 2026 by the employer.
About the role
You will own CPU core-level testbench development and verification for high-performance out-of-order RISC-V cores.
What you'll do
- Lead hands-on CPU core-level testbench development for out-of-order RISC-V cores. - Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components. - Plan and drive functional verification for CPU core features, ISA behavior, and microarchitectural scenarios. - Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components including APIC and IOMMU. - Debug regressions, close coverage, and improve core, cluster, and chip-level testbenches across simulation, emulation, and post-silicon environments. - Develop testbench and tooling infrastructure using Python orchestration across logs, waveforms, and verification databases.
What you'll need
- 8+ years in CPU verification, CPU testbench development, or closely related digital design. - Deep hands-on experience building and owning CPU core-level testbenches. - In-depth knowledge of high-performance out-of-order CPU microarchitecture. - Experience developing testbench infrastructure in CVM methodology. - Proficiency working across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams.
Skills: CPU verification, testbench development, RISC-V, UVM, RTL, functional verification
This role has been open 154 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Tenstorrent | All employers we track in this specialty (1254 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1254 |
| Open roles in the wider Digital Design & Verification family | 26 | 3328 · 115 employers |
| Median days open | 149 d | 64 d (+85 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: CPU verification, testbench development, RISC-V, UVM, RTL, functional verification
Who's hiring in this category
- Qualcomm · 120 open roles · median 43 d
- AMD · 94 open roles · median 53 d
- NVIDIA · 84 open roles · median 65 d
- Synopsys · 67 open roles · median 39 d
- SiFive · 55 open roles · median 81 d
- Cadence Design Systems · 52 open roles · median 123 d
How we counted: 1254 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.