CPU Clock Design Engineer - United States
$105,650 - $269,100 USD yearly
Originally posted 6 October 2026 by the employer.
Join a team developing clocking architecture for Intel's CPU products.
About the role
What you'll do
- Design, implement, and optimize clock distribution networks for high-performance CPU and SoC products.
- Contribute to clock architecture development and clock tree synthesis (CTS) methodologies.
- Perform timing analysis and support timing closure across complex semiconductor designs.
- Develop custom circuits, library cells, and clock-related design solutions.
- Analyze performance, power, area, and timing tradeoffs to improve product efficiency.
- Create automation solutions using scripting and programming languages to improve design productivity.
What you'll need
- Bachelor's degree in Electrical/Computer Engineering, Computer Science, or a related STEM field with 3+ years of experience OR a Master's degree in the same field with 1+ year of experience.
- Experience in Digital circuit design, VLSI design, Physical design, Clock tree synthesis (CTS), Static timing analysis (STA), Logic design, Custom circuit design, or Semiconductor design methodologies.
- Experience with one or more programming or scripting languages such as Python, Perl, TCL, or Shell.
Nice to have
- PhD in Electrical/Computer Engineering, or related field.
- Experience in clocking architecture, PLL/DLL architecture and design.
- Expertise in timing constraint adaptation and timing closure methodologies.
- Expertise in fullchip design tools and flows.
Skills: clock distribution networks, clock tree synthesis, timing analysis, VLSI design, CPU/SoC products
This role has been open 9 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 1021 |
| Open roles in the wider Digital Design & Verification family | 86 | 3204 · 115 employers |
| Median days open | 17 d | 62 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: clock distribution networks, clock tree synthesis, timing analysis, VLSI design, CPU/SoC products
Who's hiring in this category
- Qualcomm · 140 open roles · median 62 d
- Synopsys · 85 open roles · median 30 d
- AMD · 71 open roles · median 36 d
- Analog Devices · 48 open roles · median 50 d
- NVIDIA · 46 open roles · median 64 d
- NXP Semiconductors · 41 open roles · median 85 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 16 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
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