Core RTL/Microarchitecture Power Lead - CA, Santa Clara, United States
Originally posted 21 October 2026 by the employer.
Analyze and drive power-efficient microarchitecture development for Core pipelines in AMD Ryzen and EPYC CPUs.
About the role
AMD is seeking an experienced processor designer to analyze and drive power-efficient microarchitecture development for the Core pipeline in CPU designs like Ryzen and EPYC. This cross-functional role works directly with RTL, Architecture, Physical Design, and Validation teams to evaluate and optimize core power consumption.
What you'll do
- Analyze power consumption of new and existing microarchitectural features and drive development of optimizations for high-performance CPU cores. - Analyze power characteristics of Server and Client CPU workloads to guide microarchitecture decisions. - Partner with RTL teams to interpret power analysis results from tools like PTPX and collect dynamic power consumption estimates. - Coordinate with Physical Design and Design Verification teams to optimize power efficiency and create tests targeting specific core functions. - Validate silicon power consumption, reconcile discrepancies against pre-silicon models, and refine the design flow. - Partner with methodology teams to build and update power analysis tools, incorporating AI to enhance workflows.
What you'll need
- Expert-level experience in high-performance microprocessor design. - Extensive experience in low-power design techniques using industry tools in a CPU, GPU, or device of similar complexity. - Thorough understanding of microprocessor architecture, low-power design techniques, and RTL logic design.
Nice to have
- Experience with Register Transfer Level (RTL) coding for high-speed designs using Verilog or SystemVerilog. - Familiarity with performance simulators, workload analysis, and verification methods. - Experience with timing closure, physical design, synthesis, or place and route. - Experience leveraging AI and LLMs to automate workflows and assist development. - Scripting experience with Python, Perl, Ruby, or Shell. - MS degree in EE, CE, or CS with relevant industry experience.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1051
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1051 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 76 | 1051 |
| Open roles in the wider Digital Design & Verification family | 254 | 3283 · 116 employers |
| Median days open | 40 d | 62 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 150 open roles · median 57 d
- Synopsys · 84 open roles · median 35 d
- AMD (this employer) · 72 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 89 d
- NVIDIA · 40 open roles · median 62 d
How we counted: 1051 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.