Connectivity Project Engineer, Principal
$192,000 - $288,000 USD yearly
Originally posted 17 August 2026 by the employer.
Join the Qualcomm Data Center team developing high-performance, energy-efficient server solutions.
About the role
As a Principal Connectivity Project Engineer, you will be responsible for planning and executing projects through all phases from concept to commercialization across all engineering teams. This role focuses on high-performance, energy-efficient server solutions for data center applications.
What you'll do
- Oversee chipset development and ensure key performance indicators (KPIs) are met.
- Drive resolution of all engineering issues within and across various functional blocks and components of the chipset.
- Identify key risks to the project and implement mitigation strategies.
- Identify gaps in existing processes and influence the development of new methodologies.
- Report periodically to senior management on program status, progress, gaps, and risks.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field and 8+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or a related field and 7+ years of related work experience, OR PhD in Science, Engineering, or a related field and 6+ years of related work experience.
- 15 years of experience in semiconductor product development, including mixed-signal design, system design, SoC architecture, hardware design and validation, silicon test, or SoC firmware development.
- More than 10 years of experience in one or more areas of semiconductor product development.
- More than 5 years in a technical leadership role.
- Expertise in architecting, designing, and/or validating high-performance solutions in multiple functional areas of high performance SoCs, such as mixed-signal interfaces including SerDes and DDR, embedded processors, IO chiplets, power management, or high-volume manufacturing.
- Experience in one or more aspects of commercializing a chipset, including post-silicon validation, power and thermal convergence, silicon characterization and test, or compliance certifications.
- Five or more years of experience in engineering trade-off analysis.
- Demonstrated track record in hyperscale data center solutions.
Nice to have
- Experience developing high-speed Ethernet or PCIe SerDes IP or SerDes-based Ethernet or PCIe products.
Skills: planning and executing projects, semiconductor architecture, data center SoCs, mixed-signal SerDes, post-silicon validation
This role has been open 60 days — well above the 46-day median for Technical Program Management roles.
Technical Program Management · SOC Architecture
|
Open roles in category
175
|
Median days open
46 d
|
Median salary
$220k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (175 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 175 |
| Median days open | 46 d | 46 d (same as this employer) |
| Median salary (USD postings) | — | $220k |
Skills observed across this category: planning and executing projects, semiconductor architecture, data center SoCs, mixed-signal SerDes, post-silicon validation
Who's hiring in this category
- Qualcomm (this employer) · 25 open roles · median 46 d
- NVIDIA · 20 open roles · median 34 d
- AMD · 19 open roles · median 25 d
- Synopsys · 14 open roles · median 46 d
- Arm Holdings · 10 open roles · median 83 d
- Astera Labs · 6 open roles · median 67 d
How we counted: 175 open Technical Program Management (SOC Architecture) roles from 49 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.