Compiler Engineer (Mid and/or Backend) - San Jose, California, United States
Originally posted 2 March 2026 by the employer.
MLIR-based compiler infrastructure targeting custom spatial accelerator hardware.
About the role
This role focuses on transforming higher-level MLIR-based large language models by applying mid- and backend compiler techniques to target Persimmons' custom spatial accelerator hardware. You will design and optimize the compiler mid- and backend, integrate custom operations and kernels, and implement compiler passes converting intermediate representations into runtime-oriented code.
What you'll do
- Develop and enhance MLIR-based compiler pipelines targeting custom spatial accelerator hardware. - Design and optimize mid- and backend compiler techniques for lowering, graph-to-resources mapping, and code generation. - Implement transformations to convert Python, PyTorch, and similar kernel representations to LLVM IR and runtime-ready libraries. - Architect and implement support for SPMD-based distributed collective operations and lower them through specialized MLIR compiler dialects like MESH and SHARDY. - Drive loop optimizations leveraging polyhedral analysis, including loop tiling, fusion, interchange, and skewing. - Apply and optimize techniques such as bufferization, padding, inlining, register allocation, and instruction scheduling for spatial hardware.
What you'll need
- 5+ years of experience with C++ and writing clean, maintainable code. - Solid understanding and experience with MLIR framework principles, including SSA representation, interfaces, rewriting, and dialect hierarchy. - Hands-on experience developing MLIR-based compiler infrastructure and algorithms for non-GPU or custom spatial hardware architectures. - Experience lowering SIMD operations from PyTorch, Triton, xDSL, pyDSL, or Python-based frontends toward LLVM IR and SIMD kernel libraries. - Extensive experience with loop optimization based on polyhedral principles, including loop tiling, fusion, interchange, and skewing. - Experience with SPMD-based distributed collective operations, specialized MLIR compiler dialects (such as MESH and SHARDY), and collective operation lowering. - Knowledge of register allocation, instruction scheduling, bufferization, padding, inlining, and graph and tensor partitioning for spatial architectures.
Skills: MLIR-based compiler, spatial accelerator hardware, loop optimizations, code generation, hardware optimization
This role has been open 119 days — well above the 72-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
683
|
Median days open
72 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | persimmons | All employers we track in this specialty (683 roles · 75 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 683 |
| Open roles in the wider Physical Implementation family | 2 | 1489 · 110 employers |
| Median days open | 119 d | 72 d (+47 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: MLIR-based compiler, spatial accelerator hardware, loop optimizations, code generation, hardware optimization
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 149 d
- Synopsys · 62 open roles · median 40 d
- Micron Technology · 46 open roles · median 49 d
- Qualcomm · 37 open roles · median 73 d
- GlobalFoundries · 36 open roles · median 28 d
- Keysight Technologies · 34 open roles · median 76 d
How we counted: 683 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.