Communications System Architect
$141,075 - $211,613 USD yearly
Originally posted 14 July 2026 by the employer — open 58 days.
About the role
This role defines and executes a networking technology roadmap and defines and prototypes networking system solutions targeted for in-vehicle communications.
What you'll do
- Collaborate to define technology roadmaps for ADI’s automotive networking products.
- Work with FPGA designers to develop prototypes of networking functions/products.
- Lead design of new protocols for audio, video, and data transport.
- Model performance of in-vehicle communications networks.
- Support ADI standards engagement by making technical contributions to standards-development organizations.
What you'll need
- BS in Electrical, Communications, or Computer Engineering with several years of relevant experience, or MSEE/MSCE with 5+ years of experience.
- Strong knowledge of Ethernet and related protocols, communication stacks, and standards such as IEEE 1722, TSN/AVB, PTP, MACsec.
- Strong knowledge of switch architectures and traffic shaping techniques.
- Network modeling in OMNeT++ or similar tools.
- System modeling experience in Matlab/Simulink or similar tools.
Nice to have
- Experience with automotive networks such as CAN and Ethernet.
- Knowledge of other wireline communications such as PCIe.
- Knowledge of audio and video transport links/interfaces.
- Knowledge of functional safety.
- RTL design experience.
Skills: Ethernet PHY, wireline physical layer links, DSP architecture, SERDES system concepts, Matlab/Simulink modeling, digital signal processing
This role has been open 176 days — well above the 91-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
217
|
Median days open
91 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (217 roles · 44 employers) |
|---|---|---|
| Open roles in category | 4 | 217 |
| Median days open | 92 d | 91 d (+1 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: Ethernet PHY, wireline physical layer links, DSP architecture, SERDES system concepts, Matlab/Simulink modeling, digital signal processing
Who's hiring in this category
- AMD · 24 open roles · median 61 d
- Cadence Design Systems · 19 open roles · median 153 d
- Qualcomm · 17 open roles · median 74 d
- Synopsys · 16 open roles · median 53 d
- Broadcom · 11 open roles · median 142 d
- NVIDIA · 10 open roles · median 95 d
How we counted: 217 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 44 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.