Clocking Systems Engineer, Staff - Toronto, Ontario, Canada
$110,500 - $160,500 USD yearly
Originally posted 12 August 2026 by the employer.
About the role
This role involves developing DSP and mixed-signal SerDes architectures and solutions, with a focus on clock generation, clock recovery, and timing synchronization.
What you'll do
- Develop DSP and mixed-signal SerDes architectures and solutions specializing in clock generation, clock recovery, and timing synchronization.
- Develop and maintain behavioral and system-level models for PLLs, CDRs, Retimers, and clock distribution networks.
- Analyze system performance and architectural tradeoffs, identify design margins, and develop regression test frameworks.
- Support silicon bring-up and model-to-silicon correlation, including investigation of clocking-related performance issues.
- Improve simulation efficiency and engineering productivity through model optimization, code enhancements, and automation of verification and regression workflows.
- Collaborate with analog, digital, firmware, and validation teams to ensure successful implementation and integration of clocking solutions.
What you'll need
- 4 years of relevant industry experience in clocking systems, mixed-signal design, SerDes, or related areas.
- Strong understanding of Digital / mixed signal PLLs and clocking architectures.
- Strong understanding of Clock and Data Recovery (CDR) Architectures.
- Strong understanding of Jitter and phase noise analysis.
- Strong understanding of Clocking related adaptations and calibrations.
- Experience developing behavioral or system-level models using MATLAB, Python, and SystemVerilog.
Nice to have
- Master's or Ph.D. in Electrical Engineering or related field.
- Experience with DSP-based 112G, 224G, or higher-speed SerDes architectures.
- Knowledge of analog and mixed-signal PLL building blocks, including phase detectors, phase interpolators, and digitally controlled oscillators (DCOs).
- Experience with digital design and RTL development, including bit-accurate modeling.
- Experience with silicon validation and model-to-silicon correlation.
Skills: DSP and mixed-signal SerDes, clock generation, clock recovery, timing synchronization, PLLs, CDRs, Retimers
This role has been open 47 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
239
|
Median days open
76 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (239 roles · 49 employers) |
|---|---|---|
| Open roles in this specialty | 20 | 239 |
| Open roles in the wider Analog & Mixed-Signal family | 75 | 1385 · 107 employers |
| Median days open | 58 d | 76 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: DSP and mixed-signal SerDes, clock generation, clock recovery, timing synchronization, PLLs, CDRs, Retimers
Who's hiring in this category
- AMD · 28 open roles · median 64 d
- Synopsys · 26 open roles · median 44 d
- Qualcomm (this employer) · 20 open roles · median 58 d
- Cadence Design Systems · 18 open roles · median 181 d
- Apple · 12 open roles · median 7 d
- NVIDIA · 11 open roles · median 116 d
How we counted: 239 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 49 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.