Circuit Design Intern, Master's or PhD (Summer 2027) - USA - Texas - Austin, United States
$20 - $40 USD yearly
Originally posted 28 September 2026 by the employer.
About the role
This role involves performing block-level physical design using place-and-route tools and industry-standard cores to evaluate technologies, while supporting RTL analysis and simulation to validate correct implementation and benchmark power, performance, and area.
What you'll do
- Perform block-level place and route for complex cores using standard-cell and memory-library IP.
- Run RTL simulation and verification flows to confirm core implementation and support power benchmarking and design analysis.
- Apply circuit-design techniques to optimize standard-cell logic and improve IP performance, power, area, and implementation quality.
- Develop and maintain Tcl and Perl scripts that automate physical-design and RTL-simulation workflows, reporting, and data collection.
- Optimize standard-cell and memory IP through block-level design studies for Edge AI and automotive applications.
- Use industry-standard CAD and electronic design automation tools to support VLSI implementation, analysis, debugging, and documentation.
What you'll need
- Actively pursuing a Master's or PhD in Electrical Engineering, Computer Science, or a related field.
- Overall 3.0 GPA.
- English language fluency (written & verbal).
- Ability to work at least 40 hours per week during the internship.
Nice to have
- Prior related internship or co-op experience.
- Prior leadership experience in the workplace, school projects, or competitions.
- Strong interest in leveraging AI tools and emerging technologies.
- Project management skills.
- Working knowledge of UNIX operating systems.
- Coursework, research, or project experience in VLSI design, physical design, RTL simulation, standard-cell or memory IP, or semiconductor circuit design.
- Familiarity with place-and-route, RTL simulation, CAD/EDA tools, and Tcl or Perl scripting.
Skills: block-level place and route, RTL simulation, circuit-design techniques, standard-cell logic, VLSI implementation
This role has been open 12 days — well below the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1019
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1019 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 1019 |
| Open roles in the wider Digital Design & Verification family | 41 | 3166 · 114 employers |
| Median days open | 29 d | 60 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: block-level place and route, RTL simulation, circuit-design techniques, standard-cell logic, VLSI implementation
Who's hiring in this category
- Qualcomm · 139 open roles · median 60 d
- Synopsys · 86 open roles · median 24 d
- AMD · 73 open roles · median 34 d
- Analog Devices · 50 open roles · median 41 d
- NXP Semiconductors · 48 open roles · median 78 d
- NVIDIA · 46 open roles · median 64 d
How we counted: 1019 open Digital/RTL Design (RTL Design) roles from 98 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.