Circuit Design Engineer - Library/Process Monitor - Santa Clara, United States
Originally posted 5 August 2026 by the employer. Relisted by the employer on 28 October 2026.
About the role
This role leads custom digital circuits team and library development within the Digital Design Engineering group responsible for designing ASICs.
What you'll do
- Drive development of high performance, low power optimized standard cells to improve design PPA. - Drive development of optimal level shifters and retention designs that cater to low power design requirements. - Engage with CPU, SOC, and GPU teams on chip-level integration requirements. - Drive circuit QA checks and analysis, and develop new methodologies based on new design requirements. - Work with foundries on DRM compliant layout checkers and iPDK requirements. - Manage migration to new PDKs, PDV of standard cells, and design releases.
What you'll need
- Bachelor's Degree plus a minimum of 3 years of experience.
Nice to have
- 3+ years of experience in standard cells circuit development. - Proven experience in developing, driving, and implementing circuit methodologies, as well as leading and mentoring a small team. - Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, and Virtuoso. - Design experience in advanced tech node device behavior with understanding of layout rules. - Design experience in flop, complex Standard Cells design, and Power Management Cells. - Knowledge of circuit robustness analysis and experience scripting in Perl and/or TCL.
Skills: standard cells, low power design, PPA optimization, DRM/DRC/LVS, advanced tech node, Virtuoso
This role has been open 84 days — well above the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1079
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1079 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1079 |
| Open roles in the wider Digital Design & Verification family | 134 | 3357 · 116 employers |
| Median days open | 11 d | 64 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: standard cells, low power design, PPA optimization, DRM/DRC/LVS, advanced tech node, Virtuoso
Who's hiring in this category
- Qualcomm · 152 open roles · median 64 d
- Synopsys · 85 open roles · median 41 d
- AMD · 81 open roles · median 42 d
- Analog Devices · 49 open roles · median 57 d
- NXP Semiconductors · 43 open roles · median 97 d
- NVIDIA · 37 open roles · median 47 d
How we counted: 1079 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 28 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.