Chip Lead - Austin, United States
$160,650 - $298,350 USD yearly
Originally posted 10 October 2026 by the employer.
Lead the technical development and execution of complex wireless SoCs.
About the role
This role provides technical leadership for the architecture, design, integration, and execution of complex wireless System-on-Chip (SoC) products from initial product definition through silicon bring-up and production. This includes deep technical expertise in SoC architecture and microarchitecture, including processor subsystems, memory architectures, interconnects, clock and reset architectures, low-power design, digital and mixed-signal IP, and wireless connectivity.
What you'll do
- Lead the technical development and execution of complex wireless SoCs from product definition through design, silicon validation, and production.
- Define and plan SoC architecture development, including technical feasibility, implementation complexity, and IP reuse.
- Provide hands-on technical leadership throughout SoC design, integration, verification, and physical implementation.
- Drive technical readiness for tapeout, ensuring design completeness, verification closure, and resolution of critical design issues.
- Provide technical leadership during silicon bring-up, validation, characterization, and qualification.
- Drive resolution of silicon issues through design changes, firmware workarounds, or silicon revisions.
What you'll need
- 12+ years of experience with Bachelor or Master’s degree in Electrical or Computer Engineering.
- Experience in full-chip development cycle.
- Hands-on experience in architecture, micro-architecture, digital design processes.
- Knowledge of high-speed interfaces like USB, PCIe, Ethernet, Mobile DDR, Quad/Octa-SPI.
- Knowledge of peripheral interfaces like SDIO, UART, I2S, I2C, PWM, CAN.
- Knowledge of processors like RISC-V and ARM processors.
- Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure.
- Knowledge of DFT including Scan, ATPG, MBIST.
- Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling).
- Knowledge of hardware accelerators.
- Knowledge of Verilog and System Verilog.
- Knowledge of scripting languages like Perl, Python, Tcl, shell.
Skills: SoC architecture, microarchitecture, wireless SoC, silicon bring-up, low-power design, tapeout
This role has been open 0 days — well below the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
460
|
Median days open
77 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Silicon Labs | All employers we track in this specialty (460 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 460 |
| Open roles in the wider Digital Design & Verification family | 20 | 3166 · 114 employers |
| Median days open | 10 d | 77 d (−67 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: SoC architecture, microarchitecture, wireless SoC, silicon bring-up, low-power design, tapeout
Who's hiring in this category
- Qualcomm · 76 open roles · median 81 d
- NVIDIA · 60 open roles · median 64 d
- AMD · 36 open roles · median 59 d
- Apple · 34 open roles · median 4 d
- Arm Holdings · 27 open roles · median 107 d
- NXP Semiconductors · 21 open roles · median 109 d
How we counted: 460 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.