Chip Lead / ASIC Director - CA, San Jose, United States
$217,700 - $373,200 USD yearly
Originally posted 28 May 2026 by the employer.
Provide technical leadership and tapeout sign-off for Adaptive & Embedded Computing Group (AECG) device programs.
About the role
As ASIC Director – Chip Lead in the Product Development team, you will provide technical leadership and hold sign-off responsibility for device programs from conception and planning through release to manufacturing. You will oversee technical execution across Adaptive & Embedded Computing Group (AECG) device programs, directing architecture, RTL, analog and custom design, verification, physical design, timing closure, tapeout, and post-silicon validation.
What you'll do
- Lead chip definition and feasibility, identifying critical tradeoffs, architectural decisions, and key implementation decisions across schedule, cost, size, power, and floorplan. - Serve as engineering's interface to Technical Marketing to align product capabilities with customer requirements, functions, and usage modes. - Define device-specific functionality alongside marketing and architecture, and negotiate new versions or variants of IP with IP/COE leads. - Resolve technical issues and guide tradeoffs across all phases of the program, particularly in physical design. - Partner with program managers to track milestones and deliverables, resolving technical hurdles when execution diverges from planned objectives. - Communicate program changes and technical impacts across engineering, marketing, and cross-functional stakeholders.
What you'll need
- Extensive experience across the ASIC development lifecycle, spanning architecture, RTL, physical design, and tapeout. - Proven experience in a technical leadership role within a semiconductor company. - Breadth of technical depth across analog & custom design, design for test & manufacturing, verification, physical design & timing closure, and physical verification. - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
Nice to have
- FPGA technical experience. - Post-silicon validation and qualification experience. - Experience collaborating with Product Planning and Marketing teams. - Master's or PhD in Electrical Engineering, Computer Engineering, or related technical field.
Skills: ASIC development lifecycle, chip definition, architectural decisions, RTL, physical design, post-silicon validation
This role has been open 148 days — well above the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
78 d
|
Median salary
$239k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 473 |
| Open roles in the wider Digital Design & Verification family | 251 | 3328 · 115 employers |
| Median days open | 74 d | 78 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $239k |
Skills observed across this category: ASIC development lifecycle, chip definition, architectural decisions, RTL, physical design, post-silicon validation
Who's hiring in this category
- Qualcomm · 80 open roles · median 82 d
- NVIDIA · 52 open roles · median 69 d
- Apple · 37 open roles · median 16 d
- AMD (this employer) · 36 open roles · median 73 d
- Arm Holdings · 27 open roles · median 121 d
- Micron Technology · 21 open roles · median 100 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.