Cell Modeling and Verification Engineer - New College Grad 2026 - CA, Santa Clara, United States
$100,000 - $189,750 USD yearly
Originally posted 2 June 2026 by the employer. Relisted by the employer on 14 August 2026.
About the role
The NVIDIA VLSI team is looking for a Cell Modeling and Verification Engineer to develop ASIC products and ensure hardware meets design, feature, and quality objectives. The role focuses on behavioral modeling and verification for custom mixed-signal design cells used across NVIDIA SoCs and GPUs.
What you'll do
- Develop behavioral models and verification for custom mixed signal design cells used across NVIDIA products.
- Use Verilog, SystemVerilog, Perl, or Python alongside an understanding of PLL and other high-speed interconnects to model, verify, and emulate/prototype mixed-signal designs.
- Collaborate with cross-functional teams on library build, cell integration, ASIC verification, and DFT simulation.
- Document, implement, and deliver fully verified and high-performance RTL to achieve design targets.
What you'll need
- Bachelors or Masters in Electrical Engineering or Computer Engineering (or equivalent experience).
- Hands-on experience with RTL simulation and waveform debug.
- Strong understanding of Verilog HDL.
- Scripting experience and skills using Python or Perl.
- Knowledge of fundamental digital design and logic design concepts.
Nice to have
- Previous digital design experience.
- Previous experience running simulations in Verilog.
Skills: behavioral model, mixed signal design cells, PLL, high-speed interconnects, Verilog, SystemVerilog
This role has been open 200 days — well above the 96-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
|
Open roles in category
32
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Median days open
96 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (32 roles · 17 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 32 |
| Open roles in the wider Digital Design & Verification family | 229 | 3310 · 115 employers |
| Median days open | 200 d | 96 d (+104 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: behavioral model, mixed signal design cells, PLL, high-speed interconnects, Verilog, SystemVerilog
Who's hiring in this category
- Celero · 5 open roles · median 3 d
- Infineon Technologies · 4 open roles · median 49 d
- Keysight Technologies · 4 open roles · median 117 d
- Altera · 2 open roles · median 35 d
- Marvell Technology · 2 open roles · median 155 d
- NXP Semiconductors · 2 open roles · median 124 d
How we counted: 32 open Digital/RTL Design (Mixed Signal DSP) roles from 17 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.