$216,600 - $325,000 USD yearly
Originally posted 6 November 2026 by the employer.
About the role
This role leads the integration of Camera and Image Processing subsystems into SoCs within the Multimedia Camera HW team. You will provide technical leadership for subsystem-level architecture, interfaces, and integration requirements across engineering teams.
What you'll do
- Own and drive Camera subsystem-level RTL integration across multiple Camera and Image Processing IPs.
- Collaborate with hardware and system architects to define subsystem architecture, interfaces, and integration requirements.
- Own top-level integration of clocks, resets, power domains, registers/address maps, interrupts, buses/interconnects, and configuration paths.
- Run and review RTL quality checks including lint, CDC/RDC, low-power checks, connectivity checks, synthesis, and timing analysis.
- Partner with DV teams to define subsystem-level verification requirements and integration test scenarios, leading debug of issues spanning IP and subsystem/SoC boundaries.
- Drive integration methodology and automation improvements while mentoring engineers across the Camera HW team.
What you'll need
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field with 8+ years of hardware/systems experience (or Master's with 7+ years, or PhD with 6+ years).
- Experience in Verilog and SystemVerilog RTL design and debugging.
- Experience with complex ASIC and SoC subsystem integration.
- Practical knowledge of SoC bus and interconnect protocols such as AHB and AXI.
- Experience integrating clocks, resets, interrupts, registers, and power domains.
- Experience executing RTL quality methodologies including lint, CDC/RDC, synthesis, timing analysis, and low-power checks.
Nice to have
- Experience with Camera, Image Processing, Video, Multimedia, Graphics, or DSP hardware.
- Experience with ASIC implementation and integration of Camera/Image Processing IP.
- Understanding of high-bandwidth data paths, memory systems, NoC/interconnects, and performance optimization.
- Experience with low-power methodologies and UPF-based flows.
- Experience with Python, Perl, Tcl, or similar scripting languages for automation.
- Experience taking complex ASIC subsystems from architecture and RTL through verification, SoC integration, tapeout, and silicon bring-up.
Skills: RTL integration, SystemVerilog, CDC, AXI, synthesis, SoC
More semiconductor jobs: Qualcomm jobs · RTL design jobs · San Diego jobs
First seen in our index 6 days ago, well below the 67-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1058
|
Median days since first seen
67 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1058 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 147 | 1058 |
| Open roles in the wider Digital Design & Verification family | 441 | 3599 · 122 employers |
| Median days since first seen | 74 d | 67 d (−7 d vs this employer) |
| Median salary (USD postings) | n/a | $188k |
Skills observed across this category: RTL integration, SystemVerilog, CDC, AXI, synthesis, SoC
Who's hiring in this category
- Qualcomm (this employer) · 144 open roles · median 78 d
- AMD · 88 open roles · median 58 d
- Synopsys · 86 open roles · median 54 d
- NVIDIA · 48 open roles · median 69 d
- NXP Semiconductors · 44 open roles · median 108 d
- Intel Corporation · 36 open roles · median 32 d
How we counted: 1058 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 13 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.