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Velaura AI

CAD & Engineering Infrastructure Lead - Santa Clara, CA, United States

Velaura AI Santa Clara, CA, United States Full-time 2 months ago
Physical Design & EDA

$200,000 - $500,000 USD yearly

Originally posted 14 August 2026 by the employer.

Lead the integrated RTL-to-GDS flow and AI-assisted engineering workflows for Velaura AI.

About the role

This role builds and owns the engineering platform behind Velaura's silicon development, encompassing compute infrastructure, the EDA ecosystem, integrated RTL-to-GDS release flow, and AI-assisted workflows.

What you'll do

  • Define and drive engineering infrastructure requirements covering compute, storage, job scheduling, security, backup, disaster recovery, and cloud.
  • Lead AI adoption across engineering functions and drive AI-assisted workflows from pilot to standard practice.
  • Own design-flow CI/CD pipelines including orchestration, flow-release qualification, and result/QoR dashboards.
  • Provide compute, capacity, and deployment support for functional regressions, scaling to thousands of jobs per week.
  • Own the flow release process end-to-end, assembling team-owned flow content into qualified releases, regression-testing, and managing versioning, cadence, and rollback.
  • Lead the deployment and integration of EDA tools across multiple vendors, balancing productivity, quality, flexibility, and cost.
  • Own EDA licensing strategy, vendor relationships, procurement, budgets, IP administration, and license compliance.
  • Build and operate the platform for AI-assisted engineering, including model access, agentic tooling, compute capacity, and data pipelines with security and IP guardrails.

What you'll need

  • Deep understanding of the complete ASIC development lifecycle, from architecture and RTL through tapeout.
  • Experience owning CAD and infrastructure across multiple successful SoC programs.
  • Hands-on experience setting up and maintaining an integrated RTL-to-GDS flow environment, including tool/version management, foundry/IP collateral integration, and flow release/qualification.
  • Strong understanding of engineering compute infrastructure: distributed scheduling (LSF, Slurm, or equivalent), storage systems, networking, cloud environments, and license management.
  • Hands-on experience with EDA ecosystems from multiple vendors such as Synopsys, Cadence, and Siemens EDA.
  • Strong knowledge of version control, CI/CD platforms, and compute/storage patterns for high-volume regression workloads, along with reproducible engineering practices.
  • Excellent scripting and automation skills using Python, Tcl, Bash, or similar.
  • Experience evaluating and deploying AI-assisted engineering tools and workflows.

Nice to have

  • Experience scaling infrastructure in an early-stage semiconductor company.
  • Experience with advanced technology nodes with leading foundries.
  • Experience building or operating agentic AI systems, LLM-based tooling, or AI-native design automation.
  • Experience supporting chiplet-based designs or advanced packaging.

Skills: engineering infrastructure, design-flow CI/CD, EDA tools, AI-assisted engineering, RTL-to-GDS flow

Market context

This role has been open 63 days — well below the 73-day median for EDA/CAD Engineering roles.

EDA/CAD Engineering · EDA Tools

Open roles in category
675
Median days open
73 d
Median salary
$195k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Velaura AI compares in EDA/CAD Engineering hiring
Metric Velaura AI All employers we track in this specialty (675 roles · 75 employers)
Open roles in this specialty 3 675
Open roles in the wider Physical Implementation family 6 1442 · 110 employers
Median days open 37 d 73 d (−36 d vs this employer)
Median salary (USD postings) — $195k

Skills observed across this category: engineering infrastructure, design-flow CI/CD, EDA tools, AI-assisted engineering, RTL-to-GDS flow

Who's hiring in this category

  • Cadence Design Systems · 153 open roles · median 169 d
  • Synopsys · 63 open roles · median 38 d
  • Micron Technology · 44 open roles · median 46 d
  • Qualcomm · 36 open roles · median 74 d
  • GlobalFoundries · 33 open roles · median 37 d
  • Keysight Technologies · 32 open roles · median 71 d

How we counted: 675 open EDA/CAD Engineering (EDA Tools) roles from 75 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
Santa Clara, CA, United States
On-site
Full-time
$200,000 - $500,000 USD yearly
2 months ago

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