CAD Back-end Lead - Bangalore, India
Originally posted 16 September 2026 by the employer — open 2 days.
About the role
This role involves building, integrating, and supporting design flows for custom design and physical design teams. It focuses on the CAD framework supporting custom design, parasitic extraction, circuit simulation, characterization, physical implementation, timing and power analysis, physical verification, and tapeout.
What you'll do
- Develop, integrate, qualify, release, and support CAD flows spanning Custom Design, physical implementation, and Physical Verification across multiple projects and advanced process technologies.
- Own and develop reusable CAD frameworks for custom design and custom layout, as well as block-level, hierarchical, subsystem-level, and full-chip physical implementation.
- Integrate EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and other vendors into consistent, version-controlled, and reproducible design environments.
- Integrate and qualify foundry PDKs, technology files, standard-cell libraries, memories, IP collateral, RC corners, extraction decks, signoff rule decks, and EDA tool configuration files.
- Own back-end flow releases, including configuration management, regression testing, qualification, documentation, deployment, versioning, and rollback.
- Architect and develop agentic AI workflows for EDA flow orchestration, regression monitoring, failure classification, root-cause analysis, QoR comparison, knowledge retrieval, and production support.
What you'll need
- Deep understanding of the ASIC development lifecycle, with strong knowledge of custom design, physical implementation, signoff, Physical Verification, and tapeout flows.
- Experience developing and supporting CAD flows across multiple successful ASIC or SoC programs.
- Experience integrating EDA tools from Cadence, Synopsys, Siemens EDA, Ansys, and/or other major EDA vendors.
- Familiarity with tools such as Cadence Virtuoso, Innovus, Voltus, and Quantus; Synopsys Fusion Compiler, PrimeTime, StarRC, HSPICE, and PrimeSim; Siemens Calibre; and Ansys RedHawk-SC.
- Strong software-development and scripting skills using Python, Tcl, Bash, Perl, or similar languages.
- Hands-on experience with version-control and collaboration platforms such as Git, GitLab, Perforce, or equivalent tools.
- Experience developing AI- or LLM-based applications or agentic workflows that integrate tools, APIs, engineering data, and knowledge sources.
Nice to have
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, VLSI, Computer Science, or a related discipline.
- Experience enabling FinFET or Gate-All-Around process technologies.
- Experience building QoR dashboards, regression analytics, flow-monitoring systems, or automated failure-triage solutions.
- Experience deploying production-quality agentic AI workflows for semiconductor design, EDA automation, regression triage, design-data analysis, or engineering knowledge management.
- Experience developing and scaling CAD capabilities in a semiconductor company.
Skills: CAD flows, physical verification, PDKs, EDA tools, AI workflows, regression testing
This role has been open 2 days — well below the 85-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
85 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Velaura AI | All employers we track in this specialty (671 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 671 |
| Open roles in the wider Physical Implementation family | 7 | 1371 · 106 employers |
| Median days open | 22 d | 85 d (−63 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: CAD flows, physical verification, PDKs, EDA tools, AI workflows, regression testing
Who's hiring in this category
- Cadence Design Systems · 168 open roles · median 147 d
- Synopsys · 55 open roles · median 58 d
- NVIDIA · 47 open roles · median 71 d
- Micron Technology · 36 open roles · median 117 d
- Qualcomm · 34 open roles · median 71 d
- Intel Corporation · 29 open roles · median 24 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.