Back-End ASIC Engineer – Static Timing Analysis

Originally posted 6 August 2026 by the employer.

About the role

Mueon is hiring a Back-End ASIC Engineer specializing in Static Timing Analysis to drive timing closure across AI accelerators and supporting silicon. You will partner with RTL, physical design, DFT, and verification teams from block implementation through full-chip signoff.

What you'll do

• Perform static timing analysis for complex digital ASICs at block and full-chip levels across functional, test, and low-power operating modes.
• Develop, review, and maintain SDC timing constraints, including clock definitions, timing exceptions, multicycle paths, and false paths.
• Drive timing closure by identifying and resolving setup, hold, clock skew, and critical path issues alongside synthesis and physical design teams.
• Perform signoff timing analysis including MCMM verification, OCV/AOCV/POCV analysis, and signal integrity-aware timing closure.
• Support engineering change order (ECO) implementation and collaborate with clock tree synthesis teams to optimize timing quality of results.
• Develop automation and scripts using Tcl, Python, or Perl, and correlate timing analysis with gate-level simulation and post-silicon characterization.

What you'll need

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 5+ years of experience in ASIC physical design with a strong emphasis on static timing analysis.
• Extensive experience with Synopsys PrimeTime (PT/PT-SI), Cadence Tempus, or equivalent STA tools.
• Strong understanding of setup and hold analysis, clock domain crossings, timing exceptions, on-chip variation, and multi-corner multi-mode analysis.
• Experience developing and debugging SDC timing constraints for complex multi-clock designs.
• Experience with synthesis, place-and-route, and physical implementation flows using industry-standard EDA tools.
• Experience developing automation using Tcl, Python, Perl, or similar scripting languages.

Nice to have

• Experience with advanced semiconductor process technologies (7 nm and below).
• Experience supporting full-chip timing closure and tapeout for large SoCs.
• Experience with low-power implementation and UPF-aware timing analysis.
• Experience with formal timing verification or CDC verification methodologies.
• Experience correlating timing analysis with post-silicon characterization and hardware bring-up.
• Familiarity with AI accelerators, CPUs, GPUs, networking ASICs, or other high-performance computing architectures.

Skills: STA, static timing analysis, PrimeTime, timing closure, SDC

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