Automated Test Engineer - TX, Austin, United States
Originally posted 9 September 2026 by the employer.
Advance wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8.
About the role
As an Automated Test Engineer, you will develop and advance wafer-sort test infrastructure on Advantest V93000 platforms. Your work will directly improve test quality, yield, test time, scalability, and release readiness for microprocessor and chiplet products.
What you'll do
- Develop and integrate reusable wafer-sort Base Test Program and common Test Shell infrastructure.
- Lead SmarTest 8 and Advantest V93000 test program development, debug, validation, and production support.
- Drive wafer-sort strategy, first-silicon bring-up, characterization, margining, screening, diagnostics, and failure isolation for high-speed I/O and die-to-die interfaces.
- Integrate patterns, timing, levels, test methods, device configurations, binning, and debug capabilities into the common test program.
- Troubleshoot complex interactions across silicon, test software, tester and probe hardware, patterns, timing, and manufacturing processes.
- Partner with Design, Design for Test, Product Engineering, Yield Engineering, Test Hardware, and Manufacturing teams to improve coverage, testability, yield, test time, and product quality.
What you'll need
- Experience developing and debugging test programs on Advantest V93000 platforms.
- Understanding of how silicon, test software, tester and probe hardware, patterns, timing, and manufacturing processes interact.
- Strong technical judgment and disciplined software-development practices.
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- Extensive Advantest V93000 test program development and debug experience, including SmarTest 8.
- Proficiency in Java and at least one additional language, such as C++, Python, Perl, or shell scripting.
- Experience developing test flows, methods, patterns, timing, levels, diagnostics, characterization plans, and manufacturing screens.
- Experience leading or making significant architectural contributions to a Base Test Program, common Test Shell, or similar shared ATE infrastructure.
- Linux or Unix proficiency, including revision control and disciplined software-release practices.
- Experience with ORE or comparable offline simulation tools.
- Experience validating and debugging high-speed SerDes, source-synchronous, memory, or die-to-die interfaces.
- Knowledge of technologies such as PCIe, CXL, UCIe, Ethernet, JESD204, USB, DDR, HBM PHY, xGMI/Infinity Fabric, UPI, or NVLink.
- Experience with link training, equalization, lane-level diagnostics, bit-error-rate testing, jitter analysis, voltage and timing margining, or ATE-to-bench correlation.
- Knowledge of chiplet architectures, 2.5D/3D packaging, interposers, bridges, and known-good-die considerations.
- Experience using AI-enabled or agentic workflows to improve test development, debug, validation, documentation, or engineering productivity.
This role has been open 35 days — slightly above the 28-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
542
|
Median days open
28 d
|
Median salary
$172k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (542 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 542 |
| Open roles in the wider Silicon Validation & Test family | 151 | 2219 · 112 employers |
| Median days open | 39 d | 28 d (+11 d vs this employer) |
| Median salary (USD postings) | — | $172k |
Who's hiring in this category
- Teradyne · 72 open roles · median 27 d
- Renesas Electronics · 45 open roles · median 22 d
- Infineon Technologies · 41 open roles · median 37 d
- Micron Technology · 27 open roles · median 35 d
- Qualcomm · 27 open roles · median 27 d
- AMD (this employer) · 25 open roles · median 42 d
How we counted: 542 open Silicon Test Engineering (DFT Test) roles from 76 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.