ATE Test Engineering Architect - San Jose, United States
$178,500 - $331,500 USD yearly
Originally posted 27 April 2026 by the employer.
About the role
Cadence Design Systems is seeking an ATE Test Engineering Architect to lead the development and deployment of production test solutions for large complex SoCs deployed in Emulation Products. This role owns ATE test strategy and execution from first silicon bring-up through qualification and high-volume manufacturing.
What you'll do
- Lead ATE test development for wafer sort (CP) and final test (FT). - Drive first-silicon bring-up, debug, and characterization. - Define test coverage, binning, guard-banding, and production release criteria. - Analyze yield and failure data to drive test-related yield and quality improvements. - Partner with DFT, design, OSATs, and test houses to ensure manufacturable solutions. - Support qualification, production ramp, and sustained manufacturing while mentoring engineers across product teams.
What you'll need
- BS with a minimum of 12 years of experience, MS with a minimum of 10 years of experience, or PhD with a minimum of 8 years of experience. - Strong hands-on experience with CP/FT test program development. - Experience with the Advantest 93K ATE platform. - Solid understanding of DFT and silicon debug. - Proven experience supporting production and working with offshore test partners.
Skills: ATE test development, wafer sort (CP), final test (FT), Advantest 93K, DFT, silicon debug, yield analysis
This role has been open 180 days — well above the 69-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Manufacturing Equipment
|
Open roles in category
135
|
Median days open
69 d
|
Median salary
$117k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (135 roles · 37 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 135 |
| Open roles in the wider Silicon Validation & Test family | 27 | 2238 · 112 employers |
| Median days open | 180 d | 69 d (+111 d vs this employer) |
| Median salary (USD postings) | — | $117k |
Skills observed across this category: ATE test development, wafer sort (CP), final test (FT), Advantest 93K, DFT, silicon debug
Who's hiring in this category
- Infineon Technologies · 13 open roles · median 33 d
- Analog Devices · 11 open roles · median 72 d
- Keysight Technologies · 10 open roles · median 43 d
- Micron Technology · 10 open roles · median 144 d
- STMicroelectronics · 9 open roles · median 33 d
- Texas Instruments · 8 open roles · median 100 d
How we counted: 135 open Silicon Test Engineering (Manufacturing Equipment) roles from 37 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.