Associate Vice President, Engineering – DCE Connectivity Hardware
$242,080 - $362,600 USD yearly
Leading engineering execution for 200G/lane PAM4 retimers, gearboxes, and PCIe Gen7 products on 3nm FinFET and 2nm GAAFET process nodes.
Originally posted 10 November 2026 by the employer.
About the role
The Associate Vice President, Engineering leads a critical engineering function within the DCE Connectivity Hardware organization, responsible for multi-generational product execution from architecture through tape-out and high-volume production. The technical scope spans 200G/lane PAM4 retimers, gearboxes, PCIe Gen7, Active Electrical Cable solutions, Copper PHY, coherent-lite DSP, and Co-Packaged Optics on 3nm FinFET and 2nm GAAFET nodes.
What you'll do
- Lead a globally distributed engineering organization across design, verification, physical design, DFT, and silicon validation across multiple international sites.
- Own end-to-end execution of major connectivity product families from RTL design through tape-out, bringup, and production release.
- Drive first-silicon success across 200G/lane connectivity products on 3nm FinFET and 2nm GAAFET process nodes.
- Partner with architecture, systems, and product management teams to define technical roadmaps for connectivity products and evaluate new EDA tools, methodologies, and automation frameworks.
- Collaborate with analog design, physical design, firmware, software, and product engineering teams while engaging with hyperscaler and carrier customers on technical requirements.
- Build, develop, and retain the engineering organization, mentoring senior engineers and directors while directing talent reviews and succession planning.
What you'll need
- 15+ years of progressive engineering experience in semiconductor/ASIC design with a track record of leading large-scale chip programs from concept to production.
- Deep technical expertise in digital IC design (RTL/synthesis/STA), design verification and emulation, DFT, physical design, or silicon validation for high-speed connectivity products.
- Experience with advanced CMOS process nodes (7nm and below).
- Demonstrated ability to lead globally distributed engineering teams of 50+ engineers across multiple time zones.
- Track record of delivering complex, multi-million-gate ASICs on aggressive schedules with first-silicon success.
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
Skills: SerDes, PAM4, retimers, PCIe, gearboxes
More semiconductor jobs: Marvell Technology jobs · Signal integrity jobs · Santa Clara jobs
This role has been open 0 days — well below the 67-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
254
|
Median days open
67 d
|
Category median salary (all employers)
$207k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (254 roles · 52 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 254 |
| Open roles in the wider Analog & Mixed-Signal family | 23 | 1538 · 116 employers |
| Median days open | 38 d | 67 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $207k |
Skills observed across this category: SerDes, PAM4, retimers, PCIe, gearboxes
Who's hiring in this category
- Synopsys · 39 open roles · median 39 d
- AMD · 22 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 154 d
- NVIDIA · 17 open roles · median 215 d
- Qualcomm · 16 open roles · median 88 d
- Apple · 11 open roles · median 4 d
How we counted: 254 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 52 employers tracked in the SemiconductorJobs index, counted 10 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.