ASICS Design Verification Engineer-Senior
$121,800 - $182,600 USD yearly
Originally posted 19 October 2026 by the employer.
About the role
This role covers complete pre-silicon verification for digital power IPs from system-level concept through tapeout and post-silicon support. The scope includes testbench architecture, coverage, assertion model development, formal property checking, and UPF power-aware flows.
What you'll do
- Execute pre-silicon test planning, coverage development, and assertion model creation for digital power IPs. - Develop and maintain testbenches using SystemVerilog-UVM. - Implement formal verification (property checking) and deploy power-aware UPF verification flows and methodology. - Develop automation scripts to improve verification efficiency.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related work experience (or Master's degree with 1+ year, or a PhD). - 2 years of experience with ASIC design and verification tools, techniques, and methodology.
Nice to have
- Master's degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field. - 6 years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL. - 6 years of experience developing block-level testbench environments using SystemVerilog and verification methodologies such as UVM or OVM. - 6 years of experience with computer architecture fundamentals, object-oriented programming concepts, and C or C++ programming. - 6 years of experience with scripting and automation using Perl or Python. - Knowledge or experience with assertion-based formal verification. - Experience with AMBA bus protocols including AXI, AHB, or APB.
Skills: SystemVerilog, UVM, ASIC, testbench, formal verification
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1214
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1214 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 114 | 1214 |
| Open roles in the wider Digital Design & Verification family | 398 | 3244 · 116 employers |
| Median days open | 41 d | 64 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: SystemVerilog, UVM, ASIC, testbench, formal verification
Who's hiring in this category
- Qualcomm (this employer) · 113 open roles · median 40 d
- AMD · 96 open roles · median 53 d
- NVIDIA · 84 open roles · median 61 d
- Synopsys · 65 open roles · median 35 d
- SiFive · 55 open roles · median 77 d
- Cadence Design Systems · 50 open roles · median 119 d
How we counted: 1214 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 20 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.