ASIC Verification Engineer - TX, Austin, United States
Originally posted 8 October 2026 by the employer.
About the role
NVIDIA is looking for an ASIC Verification Engineer to verify global IP across multiple product lines. In this role, you will partner with design and architecture teams to develop verification test plans, maintain regressions, and achieve coverage closure for functional correctness and performance expectations.
What you'll do
- Develop test plans, tests, and verification infrastructure for verifying global IP across multiple products. - Define, develop, and automate flows and methodologies to build, deploy, and verify generated RTL. - Ensure code and functional coverage across assigned RTL. - Build verification components using SV/UVM methodology. - Drive coverage-based verification closure. - Collaborate with design teams to find corner cases and resolve verification-related issues.
What you'll need
- BS/MS in Electrical or Computer Engineering (or equivalent experience). - 2+ years of design verification experience. - Experience in pre-silicon verification (UVM, SystemVerilog), ASIC design/implementation flow, and design automation. - Programming and scripting experience in Perl or Python. - Exposure to design and verification tools, such as dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, and debug tools like Debussy or GDB.
Skills: UVM, SystemVerilog, pre-silicon verification, ASIC design/implementation flow, Perl, Python
This role has been open 200 days — below the 202-day median for Design Verification roles.
Design Verification · Mixed Signal
|
Open roles in category
52
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Median days open
202 d
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Median salary
—
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See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (52 roles · 20 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 52 |
| Open roles in the wider Digital Design & Verification family | 229 | 3310 · 115 employers |
| Median days open | 200 d | 202 d (−2 d vs this employer) |
| Median salary (USD postings) | — | — |
Skills observed across this category: UVM, SystemVerilog, pre-silicon verification, ASIC design/implementation flow, Perl, Python
Who's hiring in this category
- Cadence Design Systems · 12 open roles · median 214 d
- Qualcomm · 6 open roles · median 199 d
- Infineon Technologies · 5 open roles · median 199 d
- Retym · 5 open roles · median 94 d
- NVIDIA (this employer) · 4 open roles · median 199 d
- Microchip Technology · 2 open roles · median 221 d
How we counted: 52 open Design Verification (Mixed Signal) roles from 20 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.