ASIC Verification Engineer - New College Grad 2027 - CA, Santa Clara, United States
$100,000 - $189,750 USD yearly
Originally posted 13 October 2026 by the employer.
About the role
This role involves contributing to the design verification activities that support the pre-silicon process, ensuring proper hardware functionality. This includes simulating the RTL under a variety of conditions to identify design bugs early.
What you'll do
- Contribute to complex UVM testbench environments, including test development, automation, or analysis.
- Develop directed or random tests in SystemVerilog to verify reference C++ and RTL models in a simulation environment.
- Debug RTL simulation failures.
- Employ AI technologies to create automated systems and flows.
What you'll need
- Pursuing or recently completed a BS, MS, or PhD in EE, CE, or related field (or equivalent experience).
- Coursework or prior internship exposure to computer architecture, logic design, and/or HDL languages (Verilog, VHDL).
- Strong programming experience in C++ or SystemVerilog and general understanding of OOP concepts.
- Solid understanding of basic concepts of CPU or SoC architecture.
- Exceptional analytical skills and problem-solving skills.
Skills: ASIC Verification, pre-silicon, UVM testbench, SystemVerilog, RTL simulation
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 82 | 1187 |
| Open roles in the wider Digital Design & Verification family | 237 | 3192 · 115 employers |
| Median days open | 56 d | 64 d (−8 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: ASIC Verification, pre-silicon, UVM testbench, SystemVerilog, RTL simulation
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA (this employer) · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.