ASIC Verification Engineer - CA, Santa Clara, United States
$116,000 - $218,500 USD yearly
Originally posted 28 July 2026 by the employer.
NVIDIA’s Clocks team is looking for an experienced ASIC Design Verification engineer.
About the role
This role involves validating clocking and reset logic within NVIDIA's Clocks Team to ensure high-quality delivery for various units in SOC and GPU ASICs. You will contribute to verifying complex clocks designs that power product lines ranging from Data Centers, Consumer graphics, to Self-driving cars and artificial intelligence.
What you'll do
- Own validation of Clocking structures in Tegra and GPU products from start to finish.
- Develop test plans, automation, validation flows, and coverage metrics.
- Perform test execution, bug identification/fix, and productization.
- Develop scalable solutions for complex problems.
- Partner with clocks architecture and design teams to validate clock designs.
What you'll need
- BS or MS in EE/ECE or equivalent experience.
- 3+ years of proven design verification experience.
- Understanding of Logic Design and Architecture.
- Expertise in SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop.
- Exposure to block level and system-level verification.
- Strong coding skills in System Verilog, Perl, Python, and C++.
- Prior experience in implementing Test plans for pre-silicon platforms.
Skills: ASIC Design Verification, verification flows, System Verilog, UVM, test plan development
This role has been open 82 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 84 | 1202 |
| Open roles in the wider Digital Design & Verification family | 230 | 3201 · 115 employers |
| Median days open | 60 d | 65 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: ASIC Design Verification, verification flows, System Verilog, UVM, test plan development
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA (this employer) · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.