ASIC Power Engineer - Irvine, United States

Originally posted 27 October 2026 by the employer.

Focus on low-power architecture, power modeling, and validation for wireless communication SoC designs using PTPX and Power Artist.

About the role

As an ASIC Power Engineer on the wireless silicon development team, you will focus on low power architecture, power modeling, and silicon correlation. The role covers power modeling, analysis, and silicon validation tasks for wireless communication SoC designs.

What you'll do

- Execute power modeling, power analysis, and silicon validation for wireless communication SoC designs. - Drive low-power architecture, pre-silicon power estimation, and correlation efforts across wireless silicon. - Apply power analysis methodologies to evaluate energy efficiency across SOC components. - Correlate pre-silicon power models with post-silicon measurement data.

What you'll need

- BS degree and a minimum of 10 years of relevant industry experience. - In-depth ASIC power knowledge and understanding of ASIC logic design. - Hands-on experience with power tools such as PTPX and Power Artist. - Knowledge of low power design techniques and UPF. - Proficiency in scripting languages, including Shell, Perl, or Python. - Knowledge of common SOC components, including CPU, fabric, peripherals, and PCIe.

Nice to have

- Pre-silicon power estimation and pre-silicon power modeling experience. - Wireless domain knowledge, including Wi-Fi, BT, and UWB. - System architecture experience. - Post-silicon power correlation experience.

Skills: low power architecture, power modeling, PTPX, Power Artist, UPF