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NVIDIA

ASIC Physical Design Engineer - Shanghai, China

NVIDIA China, Shanghai, China Full-time 1 day ago
Physical Design & EDA

Originally posted 5 October 2026 by the employer.

About the role

This role involves physical design tasks from RTL to GSDII, encompassing design quality checks, synthesis, formal checks, partitioning, constraint definition, asynchronous checks, and timing analysis/fixing/signoff. You will work on advanced processes and technology for large-scale chips.

What you'll do

  • Perform STA for hierarchical designs.
  • Create and validate constraints, and manage timing budgets.
  • Achieve timing closure for both partition and full chip levels.
  • Conduct special timing closure, including I/O, test, and clock.
  • Perform synthesis, netlist quality checks, and Formal Verification.
  • Implement chip partitioning and floorplan.
  • Create function ECOs.
  • Develop and enhance the entire timing closure flow from frontend to backend.
  • Develop flow automation and methodology in physical design areas.

What you'll need

  • MS in EE, CS or Microelectronics with 1+ year experience.
  • Project experience in IC design implementation.
  • Courses taken in circuit design, digital design.
  • Hand-on experience in EDA software from Synopsys (FC/DC/PT/Formality), Cadence (RC compiler/Genus/LEC).
  • Proficient in English reading and writing.

Nice to have

  • Proficient user of Perl, Python or TCL.
  • Excellent English communication skill.

Skills: STA, timing closure, floorplan, synthesis, Formal Verification

Market context

This role has been open 0 days — well below the 60-day median for Physical Design roles.

Physical Design · Physical Design

Open roles in category
631
Median days open
60 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How NVIDIA compares in Physical Design hiring
Metric NVIDIA All employers we track in this specialty (631 roles · 78 employers)
Open roles in this specialty 39 631
Open roles in the wider Physical Implementation family 87 1430 · 108 employers
Median days open 60 d 60 d (same as this employer)
Median salary (USD postings) — $185k

Skills observed across this category: STA, timing closure, floorplan, synthesis, Formal Verification

Who's hiring in this category

  • Qualcomm · 122 open roles · median 38 d
  • AMD · 49 open roles · median 21 d
  • Broadcom · 40 open roles · median 85 d
  • NVIDIA (this employer) · 37 open roles · median 60 d
  • Synopsys · 29 open roles · median 48 d
  • Micron Technology · 25 open roles · median 75 d

How we counted: 631 open Physical Design (Physical Design) roles from 78 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.

Apply now
China, Shanghai, China
On-site
Full-time
1 day ago

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