ASIC Implementation Engineer PD - USA-CA San Jose Innovation Drive, United States
$121,900 - $195,000 USD yearly
Originally posted 16 July 2026 by the employer.
Work on top level floorplanning and physical design for Artificial Intelligence and PCIe Switch Products.
About the role
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the ASIC Products Division. The position involves taking RTL to silicon tape-out for Artificial Intelligence and PCIe Switch Products.
What you'll do
- Own chip floorplanning, partition creation, clock tree, and delivery of top level partitions. - Resolve physical design issues related to chip integration and assembly. - Manage cross-functional interactions related to top level floorplanning, I/O, and bump planning with the package team. - Develop and improve floorplan implementation methodologies using both industry and internal tools. - Perform technical evaluations of vendors and IP, providing recommendations and assessments to meet design specifications.
What you'll need
- Bachelor's degree in Electrical Engineering with 8+ years of experience, or Master's degree in Electrical Engineering with 6+ years of experience in top level floorplanning focused on die size estimate, partitioning, clocking, and pin planning. - Experience resolving chip level DRC/LVS/EMIR issues for advance nodes. - Experience with bump planning, RDL implementation, and multi-voltage domain designs. - Experience with hierarchical floorplanning, power grid design, structured clocks, top level pipeline planning, and custom routes. - Scripting experience in Python, Tcl, or Perl alongside EDA tools. - Ability to work in person at the San Jose site.
Nice to have
- Experience working on technologies including Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, and chiplets.
Skills: floorplanning, physical design, ASIC, RTL to silicon, DRC/LVS/EMIR
This role has been open 96 days — well above the 61-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
656
|
Median days open
61 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (656 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 656 |
| Open roles in the wider Physical Implementation family | 41 | 1450 · 110 employers |
| Median days open | 100 d | 61 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: floorplanning, physical design, ASIC, RTL to silicon, DRC/LVS/EMIR
Who's hiring in this category
- Qualcomm · 119 open roles · median 44 d
- AMD · 61 open roles · median 26 d
- Synopsys · 38 open roles · median 35 d
- Intel Corporation · 36 open roles · median 14 d
- NVIDIA · 36 open roles · median 70 d
- Broadcom (this employer) · 32 open roles · median 100 d
How we counted: 656 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.