ASIC Front-End Methodology Engineer - Hyderabad-Sattva, India
Originally posted 21 September 2026 by the employer — open 0 days.
About the role
This role drives consistency, scalability, and quality across ASIC front-end implementation flows spanning multiple chiplets, subsystems, and SoCs.
What you'll do
- Own and drive front-end methodology alignment across multiple chiplets, subsystems, and SoC programs.
- Manage tool qualification, deployment, version control, and migration strategies across projects.
- Develop, maintain, and govern front-end flow infrastructure, methodology guidelines, and design rulesets.
- Partner with CAD teams to evaluate, deploy, and support new methodologies, EDA tools, and automation solutions.
- Coordinate with Design, Physical Design, DFT, Verification, and Architecture teams to ensure methodology requirements are understood and implemented consistently.
- Lead cross-functional technical reviews, alignment meetings, and customer-facing discussions related to methodology, flow readiness, and tool deployment.
What you'll need
- Strong experience in ASIC front-end implementation methodologies and EDA tool flows.
- Experience managing tool versions, methodology releases, rulesets, and multi-project flow deployments.
- Understanding of RTL-to-GDS implementation flows, including synthesis, constraints, CDC, lint, DFT, STA, and physical design interactions.
- Experience working across multiple IPs, subsystems, chiplets, or SoC programs with methodology governance responsibilities.
- Experience developing automation, scripting, dashboards, or AI-enabled solutions for flow management and quality improvement.
- Bachelor's degree with 8+ years of experience, or Master's degree with 6+ years of experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- Familiarity with configuration management systems, regression infrastructure, release processes, and tool qualification methodologies.
- Experience defining methodology standards, signoff requirements, and best practices for large-scale ASIC programs.
- Interest in AI/ML-driven productivity solutions, automation, and design methodologies.
- Experience working directly with internal customers and cross-functional executive stakeholders.
Skills: Front-End Methodology, FlowCzar, tool qualification, flow infrastructure, RTL-to-GDS implementation flows
This role has been open 0 days — well below the 87-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
671
|
Median days open
87 d
|
Median salary
$195k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (671 roles · 74 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 671 |
| Open roles in the wider Physical Implementation family | 61 | 1382 · 107 employers |
| Median days open | 75 d | 87 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $195k |
Skills observed across this category: Front-End Methodology, FlowCzar, tool qualification, flow infrastructure, RTL-to-GDS implementation flows
Who's hiring in this category
- Cadence Design Systems · 169 open roles · median 146 d
- Synopsys · 55 open roles · median 60 d
- NVIDIA · 46 open roles · median 65 d
- Micron Technology · 35 open roles · median 122 d
- Qualcomm · 34 open roles · median 73 d
- Intel Corporation · 29 open roles · median 26 d
How we counted: 671 open EDA/CAD Engineering (EDA Tools) roles from 74 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.