ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) - North Reading, MA, United States

Originally posted 30 September 2026 by the employer.

About the role

This role focuses on FPGA verification, working with cross-functional teams to deliver high-quality, robust designs. The primary focus is FPGA verification.

What you'll do

• Review design requirements and specifications
• Write and review verification plans
• Develop testbench architecture and implementation
• Create reference models
• Write System Verilog tests and develop UVM environments; perform debug
• Collect, merge, and close functional and code coverage
• Manage bugs and issues using a tracking tool
• Collaborate with logic designers
• Communicate technical status and risks to the team leader

What you'll need

• 3+ years of professional experience in digital logic verification or related roles
• Experience with Cadence Xcelium or other industry-standard simulators
• Strong experience with System Verilog and Universal Verification Methodology (UVM)
• Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
• Experience with RTL design using Verilog HDL
• Familiarity with System Verilog assertion-based verification methodologies
• Experience working within CI/CD development flows