ASIC Formal Verification Engineer I, Annapurna Labs - Austin, Texas, United States
Originally posted 22 October 2026 by the employer.
Focus on formal verification for Machine Learning acceleration silicon using Verilog and System Verilog Assertions (SVA).
About the role
As an ASIC Formal Verification Engineer I on the Machine Learning Acceleration team at Annapurna Labs, you will define and verify specifications of critical hardware modules using formal methods and industrial model checkers.
What you'll do
- Understand requirements of specific hardware blocks and write functional descriptions of correct behavior. - Write modeled specifications using hardware description languages including Verilog and System Verilog Assertions (SVA). - Use industrial model checkers to prove that hardware under design matches modeled specifications. - Apply proof techniques including modeling abstractions and inductive reasoning. - Implement automation techniques and scripting flows to support formal proof workflows.
What you'll need
- Experience or coursework in hardware description languages such as Verilog. - Knowledge of System Verilog Assertions (SVA) for writing functional specifications. - Familiarity with formal verification methods or industrial model checkers. - Understanding of digital pre-silicon hardware design concepts.
Skills: formal verification, System Verilog Assertions, SVA, model checkers, Verilog
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1233 |
| Open roles in the wider Digital Design & Verification family | 23 | 3298 · 115 employers |
| Median days open | 22 d | 64 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: formal verification, System Verilog Assertions, SVA, model checkers, Verilog
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.