ASIC Floorplan Design Engineer - New College Grad 2026 - CA, Santa Clara, United States
$116,000 - $218,500 USD yearly
Originally posted 31 August 2026 by the employer.
Design and implement ASIC floorplans for GPU and SoC development.
About the role
As an ASIC Floorplan Design Engineer, you will design and implement floorplans for SoCs and GPUs.
What you'll do
- Develop and optimize floorplans during early chip development.
- Drive the area review process and collaborate with the ASIC design team.
- Solve timing and routing congestion issues with physical and ASIC design teams.
- Build tools and improve existing infrastructure to optimize chip area and execution speed.
What you'll need
- Master's Degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
- Hardware engineering background with a concentration in VLSI and/or Computer Architecture.
- Experience in Verilog, System Verilog, or similar HVL.
- Experience with CAD and physical design methodologies, chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
- Experience with Python, Perl, and C/C++ programming languages.
Skills: ASIC Floorplan, GPU and SoC, power/clock distribution, P&R and timing closure
This role has been open 43 days — well below the 63-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 664 |
| Open roles in the wider Physical Implementation family | 87 | 1463 · 108 employers |
| Median days open | 68 d | 63 d (+5 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC Floorplan, GPU and SoC, power/clock distribution, P&R and timing closure
Who's hiring in this category
- Qualcomm · 122 open roles · median 46 d
- AMD · 59 open roles · median 21 d
- NVIDIA (this employer) · 39 open roles · median 68 d
- Broadcom · 35 open roles · median 93 d
- Synopsys · 35 open roles · median 44 d
- Intel Corporation · 29 open roles · median 14 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.