ASIC Engineer I, Annapurna Labs, Early Career - 2027 - Cupertino, California, United States
Originally posted 24 September 2026 by the employer.
Annapurna Labs designs custom silicon at Amazon, including Graviton, Trainium, Inferentia, and the Nitro system.
About the role
This role involves contributing to real chip development work as an ASIC Engineer I within Annapurna Labs. The work focuses on custom silicon for Graviton, Trainium, Inferentia, and the Nitro system.
What you'll do
- Design and implement RTL for digital logic blocks using Verilog/SystemVerilog.
- Develop and run verification environments to validate design functionality and coverage.
- Support synthesis, timing analysis, and physical design flows.
- Debug design issues through simulation and analysis.
- Collaborate with architecture, verification, and physical design teams.
- Document design decisions and present work to the team.
What you'll need
- Experience with RTL design for machine learning accelerators (Trainium/Inferentia).
- Experience with design verification and functional validation.
- Experience with physical design, timing closure, and place-and-route.
- Experience with SoC integration and chip architecture.
- Experience with Verilog/SystemVerilog.
Skills: RTL design, Verilog/SystemVerilog, machine learning accelerators, design verification, physical design
This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
972
|
Median days open
63 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (972 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 972 |
| Open roles in the wider Digital Design & Verification family | 20 | 3097 · 114 employers |
| Median days open | 26 d | 63 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: RTL design, Verilog/SystemVerilog, machine learning accelerators, design verification, physical design
Who's hiring in this category
- Qualcomm · 147 open roles · median 48 d
- AMD · 66 open roles · median 65 d
- Synopsys · 59 open roles · median 20 d
- NXP Semiconductors · 53 open roles · median 70 d
- Analog Devices · 49 open roles · median 54 d
- NVIDIA · 48 open roles · median 48 d
How we counted: 972 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.