ASIC Emulation Engineer - CA, Santa Clara, United States
Originally posted 10 September 2026 by the employer.
This role focuses on emulation of complex networking subsystems and SoCs using ZeBu, Veloce, and Palladium platforms.
About the role
This role involves leading emulation of complex networking subsystems and SoCs. You will work on technologies spanning high-speed Ethernet, PCIe, DMA, RDMA, packet processing, traffic management, embedded processors, firmware, and system use cases.
What you'll do
- Define emulation strategy for complex networking IP, subsystems, and SoCs.
- Bring up and deploy designs on ZeBu, Veloce, Palladium, or equivalent platforms.
- Enable firmware boot, driver development, operating-system bring-up, and system-level workloads prior to silicon.
- Validate networking and I/O subsystems including Ethernet, PCIe, DMA, RDMA, packet processing, and traffic management.
- Debug complex issues across RTL, emulation infrastructure, firmware, drivers, and software stacks.
- Drive workload enablement, regression health, failure triage, and validation closure.
What you'll need
- Strong hands-on experience with ZeBu, Veloce, Palladium, or equivalent hardware emulation platforms.
- Strong debug skills spanning RTL, firmware, software, and system-level interactions.
- Experience with transactors, emulation environments, and hardware-software co-verification.
- Proficiency in C/C++, Python, Tcl, Shell, or equivalent scripting languages.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Nice to have
- Experience with high-speed Ethernet, RDMA/RoCE, PCIe Gen5/Gen6, or advanced networking architectures.
- Experience with packet-processing pipelines, switch fabrics, traffic managers, schedulers, or QoS architectures.
- Experience with performance validation, silicon bring-up, diagnostics, or post-silicon debug.
- Experience leading technical projects and mentoring engineers.
Skills: ASIC Emulation Engineer, ZeBu, Veloce, Palladium, hardware-software co-verification
This role has been open 34 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 97 | 1192 |
| Open roles in the wider Digital Design & Verification family | 255 | 3191 · 115 employers |
| Median days open | 50 d | 65 d (−15 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: ASIC Emulation Engineer, ZeBu, Veloce, Palladium, hardware-software co-verification
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD (this employer) · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.