ASIC DTCO, Timing and Technology Engineer
$140,000 - $210,000 USD yearly
Originally posted 28 July 2026 by the employer.
This role focuses on DTCO analysis for Mobile, Compute, Automotive and IOT markets.
About the role
This role focuses on DTCO and timing analysis to evaluate process technology entitlement (PPAY) for SOC products at the block/IP-level and at system-level. The work involves advanced process technologies including 5nm, 4nm, 2nm and beyond.
What you'll do
- Perform DTCO analysis targeting Mobile, Compute, Automotive and IOT markets.
- Evaluate process technology entitlement (PPAY) for SOC products at block/IP-level and system-level.
- Conduct Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for power and performance validation.
- Execute STA sign off using PT/PT-SI and Tempus.
- Perform block level PPA analysis/implementation (RTL to GDS flow) for hard macros.
- Drive Fmax optimization, PPAY, and cost improvements/reduction with foundry DTCO team, EDA companies, CAD team, and IP team.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 3+ years of experience, OR PhD in Science, Engineering, or related field and 2+ years of experience.
- Experience with methodologies, tools, and implementation flows/technologies for process technology evaluation.
- Proficiency in Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre).
- Experience with STA sign off using PT/PT-SI and Tempus.
- Knowledge of block level PPA analysis/implementation (RTL to GDS flow) using FC Synthesis, FC Place and Route, Genus, and Innovus.
- Programming skills in Python, Perl, TCL, Unix shell, C/C++.
Nice to have
- ML modeling experience.
Skills: ASIC design, timing, DTCO, technology engineer
This role has been open 81 days — well above the 60-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1037
|
Median days open
60 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1037 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 140 | 1037 |
| Open roles in the wider Digital Design & Verification family | 381 | 3201 · 115 employers |
| Median days open | 64 d | 60 d (+4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC design, timing, DTCO, technology engineer
Who's hiring in this category
- Qualcomm (this employer) · 140 open roles · median 64 d
- Synopsys · 86 open roles · median 32 d
- AMD · 71 open roles · median 38 d
- Analog Devices · 47 open roles · median 50 d
- NVIDIA · 44 open roles · median 60 d
- NXP Semiconductors · 42 open roles · median 86 d
How we counted: 1037 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.