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Synopsys

ASIC Digital Design, Sr Staff Engineer - 18603

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Sunnyvale, California, United States 1 month ago
Digital Design & SoC Architecture

Originally posted 2 September 2026 by the employer.

Contribute to LPDDR PHY IP that powers mobile and AI applications in production silicon worldwide.

About the role

This role involves extensive ASIC digital design with a track record of delivering production RTL for complex semiconductor IP, encompassing timing closure, power optimization, and design quality across advanced process nodes.

What you'll do

  • Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
  • Optimize designs to meet timing, power, and area targets across multiple process nodes
  • Develop Perl automation for design generation and flow integration
  • Collaborate with cross-functional teams to resolve timing and power challenges
  • Contribute to design reviews and methodology development

What you'll need

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
  • 8+ years of ASIC digital design experience with RTL ownership in production silicon
  • Expert Verilog proficiency for timing-critical designs
  • Strong Perl scripting skills for design automation
  • Deep knowledge of synthesis, timing analysis, and power optimization

Nice to have

  • Experience with PHY IP or high-speed interfaces is preferred
Market context

This role has been open 41 days — well below the 61-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1021
Median days open
61 d
Median salary
$185k
See the full market breakdown ▾Category comparison, and who else is hiring
How Synopsys compares in Digital/RTL Design hiring
Metric Synopsys All employers we track in this specialty (1021 roles · 103 employers)
Open roles in this specialty 84 1021
Open roles in the wider Digital Design & Verification family 167 3188 · 115 employers
Median days open 29 d 61 d (−32 d vs this employer)
Median salary (USD postings) — $185k

Who's hiring in this category

  • Qualcomm · 134 open roles · median 64 d
  • Synopsys (this employer) · 86 open roles · median 29 d
  • AMD · 72 open roles · median 35 d
  • Analog Devices · 49 open roles · median 47 d
  • NVIDIA · 46 open roles · median 63 d
  • NXP Semiconductors · 41 open roles · median 84 d

How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Sunnyvale, California, United States
On-site
1 month ago

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